EP0386337A2
Expired / Lapsed
EP
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Multistep planarized chemical vapor deposition process
Assignee: Applied Materials Inc
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Filing: 1989-12-15
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Granted: —
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Expires: 2009-12-15
Abstract
Abstract An improved planarization process is disclosed which comprises depositing over a patterned integrated circuit structure (2) on a semiconductor wafer (10) a conformal insulation layer (20) by ECR plasma deposition of an insulation materia. The ECR plasma deposition is carried out until the trenches or low regions between adjacent raised portions of the structure are completely filled with insulation material. A planarization layer (30) of a low melting glass material, such as a boron oxide glass, is then formed over the integrated circuit structure (2) to a depth or thickness sufficient to cover the highest portions of the ECR plasma deposited insulation layer (20). This planarization layer (30) is then anisotropically etched back sufficiently to provide a planarized surface on the ECR plasma deposited insulation layer. A further layer (40) of insulation material may then be conventionally CVD deposited over the planarized ECR plasma deposited insulation layer (30) which acts to encapsulate any remaining portions of the planarizing layer (30).
Inventors
- 👤 Dan Maydan
- 👤 David Nin-Kou Wang
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 18:30
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/6922; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/66; H10P14/662; H10P14/6923; H10P95/00; H10P95/06; H10P95/062; H10P95/064; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092; H10P14/6336; H10P14/69215; Y; Y10; Y10S; Y10S148/00; Y10S148/133; Y10S438/00; Y10S438/907; Y10S438/908
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
69 words
A process for planarization of an integrated circuit structure in a vacuum apparatus, said structure having portions on the surface thereof higher than adjacent portions of the surface which comprises: a) depositing a conformal insulation layer over said substrate using an ECR plasma deposition; b) depositing a low melting inorganic planarization layer over said conformal insulation layer; and c) etching said planarization layer to planarize said integrated circuit structure.
Claim 2
Dependent Claim
69 words
A process for planarization of an integrated circuit structure in a vacuum apparatus, said structure having portions on the surface thereof higher than adjacent portions of the surface which comprises: a) depositing a conformal insulation layer over said substrate using an ECR plasma deposition; b) depositing a low melting inorganic planarization layer over said conformal insulation layer; and c) etching said planarization layer to planarize said integrated circuit structure.
Claim 3
Dependent Claim
26 words
The process of claim 1 which comprises the further step of depositing preferably CVD deposition, a further insulation layer over said structure after said planarization step.
Claim 4
Dependent Claim
45 words
The process of claim 1 or 2, wherein said step of ECR plasma depositing said insulating layer further comprises depositing a layer of insulation material over said integrated circuit structure selected from the class consisting of silicon oxide, silicon oxynitride, silicon nitride, and phosphorus silicate.
Claim 5
Dependent Claim
58 words
The process of claim 1, 2, or 3, wherein said ECR plasma deposition is carried out while maintaining a magnetic flux density of from about 500 to about 2500 gauss, a microwave frequency to form the plasma ranging from about 1 to about 4 GHz, and a plasma power level of from about 100 to about 1500 watts.
Claim 6
Dependent Claim
55 words
The process of any preceding claim, wherein said ECR plasma deposition is carried out while maintaining the temperature of said deposition at from about 25° C to about 400° C, preferably about 300° C to about 500° C, and a pressure ranging from about 0.05 to about 20 millitorr, preferably about 2 to 30 torr.
Claim 7
Dependent Claim
46 words
The process of any preceding claim, wherein said step of depositing said inorganic planarizing layer further comprises depositing an inorganic planarizing layer capable of being etched at about the same rate as said insulating layer and having a flow temperature of not greater than 500° C.
Claim 8
Dependent Claim
50 words
The process of preceding claim wherein said step of depositing said low melting inorganic planarizing layer further comprises depositing an inorganic planarizing layer consisting essentially of one or more low melting glasses selected from the class consisting of B₂O₃, B₂S₆, B₂O₃/SiO₂ mixtures, As₂O₃, As₂S₃, P₂O₅ and combinations thereof, preferably B₂O₃.
Claim 9
Dependent Claim
35 words
The process of any preceding claim, wherein said step of etching said planarization layer to planarize said integrated circuit structure further comprise anisotropically dry etching said structure without removing said structure from said vacuum apparatus.
Claim 10
Dependent Claim
166 words
Vacuum apparatus for deposition and planarization of an integrated circuit structure (2) on a semiconductor wafer (10) having portions (14) on the surface thereof higher than adjacent portions (16) of the surface which comprises: a) ECR plasma deposition means including an ECR plasma deposition chamber (102-108) for depositing a conformal insulation layer (20) over said integrated circuit structure (2) on said wafer (10); b) deposition means, including the same or a different chamber (102-108) in said apparatus (100), for depositing a low melting inorganic planarization layer (30) over said conformal insulation layer (20)' c) etching means, including the same or a different chamber (102-108) in said apparatus, for anisotropically dry etching said planarization layer (30) to planarize said integrated circuit structure (2); and d) means (120;122,130,134) for moving said wafer (10) within said vacuum apparatus (100) from one of said chamber (e.g. 102) to another (e.g. 104) without removing said wafer (10) from said vacuum apparatus (100) to reduce contamination of said integrated circuit structure (2).
Claim 11
Dependent Claim
166 words
Vacuum apparatus for deposition and planarization of an integrated circuit structure (2) on a semiconductor wafer (10) having portions (14) on the surface thereof higher than adjacent portions (16) of the surface which comprises: a) ECR plasma deposition means including an ECR plasma deposition chamber (102-108) for depositing a conformal insulation layer (20) over said integrated circuit structure (2) on said wafer (10); b) deposition means, including the same or a different chamber (102-108) in said apparatus (100), for depositing a low melting inorganic planarization layer (30) over said conformal insulation layer (20)' c) etching means, including the same or a different chamber (102-108) in said apparatus, for anisotropically dry etching said planarization layer (30) to planarize said integrated circuit structure (2); and d) means (120;122,130,134) for moving said wafer (10) within said vacuum apparatus (100) from one of said chamber (e.g. 102) to another (e.g. 104) without removing said wafer (10) from said vacuum apparatus (100) to reduce contamination of said integrated circuit structure (2).
Claim 12
Dependent Claim
42 words
The apparatus of claim 9, wherein said means for moving said semiconductor wafer (10) within said vacuum apparatus (100) from one chamber (102) to another (104) include interlock means (110,116) interconnecting one chamber (102) in said vacuum apparatus (100) with another chamber.
Claim 13
Dependent Claim
55 words
The apparatus of claim 9 or 10, wherein said means for moving said semiconductor wafer (10) within said vacuum apparatus (100) from one chamber (120) to another (104) further include robotic means (120;122,130,134) within said vacuum apparatus (100) capable of moving a semiconductor wafer (10) from one chamber in said vacuum apparatus to another chamber.
References Cited (Backward Citations)
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