EP0385389A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor integrated circuit memory enabling memory write masking
Assignee: Micron Memory Japan Ltd
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Filing: 1990-02-27
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Granted: —
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Expires: 2010-02-27
Abstract
Abstract Write data lines and write amplifier enable signal lines are connected to write amplifiers of a semiconductor memory device which can be switched between one-bit input and output mode configuration and multi-bit input and output mode configuration by the shared use of a pellet. A write mask data for memory write mask is supplied to the write amplifiers by the write amplifier enable signal lines.
Inventors
- 👤 Kazuhiro Nakada
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 22:01
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1078; G11C7/1084; G11C7/1006
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
165 words
A semiconductor memory device adapted for use by switching in one-bit input and output mode as well as multi-bit input and output mode by making shared use of a pellet, and for execution of a memory write masking, comprising: a memory cell array; a write amplifier for operatively performing a data write operation to said memory cell array; a write data line connected to said write amplifier for supplying a write data; a write amplifier enable signal line connected to said write amplifier for controlling the activation of said write amplifier; means for receiving from the outside a write mask data for designating write mask for each bit at the time of said multi-bit input and output mode configuration; and means connected to said receiving means and said write amplifier enable signal line for supplying a write mask data received by said receiving means from the outside to said write amplifier enable signal line at the time of said multi-bit input and output mode configuration.
Claim 2
Dependent Claim
165 words
A semiconductor memory device adapted for use by switching in one-bit input and output mode as well as multi-bit input and output mode by making shared use of a pellet, and for execution of a memory write masking, comprising: a memory cell array; a write amplifier for operatively performing a data write operation to said memory cell array; a write data line connected to said write amplifier for supplying a write data; a write amplifier enable signal line connected to said write amplifier for controlling the activation of said write amplifier; means for receiving from the outside a write mask data for designating write mask for each bit at the time of said multi-bit input and output mode configuration; and means connected to said receiving means and said write amplifier enable signal line for supplying a write mask data received by said receiving means from the outside to said write amplifier enable signal line at the time of said multi-bit input and output mode configuration.
Claim 3
Dependent Claim
114 words
A semiconductor memory device as claimed in claim 1, wherein said memory cell array is subdivided spatially into a plurality of many cell array parts, said write amplifier are included in number equal to that of said write amplifiers, arranged in the vicinity of the respective memory cell array parts, said write data line and said write amplifier enable signal line are connected in series to each of the plurality of write amplifiers, said receiving means receives from the outside a write mask data having pieces of binary information equal in number to that of said write amplifier enable signal lines, and said supply means is arranged in the vicinity of said receiving means.
Claim 4
Dependent Claim
92 words
A semiconductor memory device as claimed in claim 2, wherein said device further includes means for receiving a control signal for designating the difference between said one-bit input and output mode configuration and said multi-bit input and output mode configuration and supplying means includes a selection circuit which selects one of said write amplifier enable signal lines at the time of said one-bit input and output mode configuration, and outputs said write mask data to said write amplifier enable signal lines at the time of said multi-bit input and output mode configuration.
Claim 5
Dependent Claim
77 words
A semiconductor memory device as claimed in claim 3, wherein said selection circuit includes a write mask decoder which decodes address signals supplied from the outside and activates one of said write amplifier enable signal lines at the time of said one-bit input and output mode configuration, and outputs said write mask data from said receiving means, as they are, to said write amplifier enable signal lines at the time of multi-bit input and output mode configuration.
Claim 6
Dependent Claim
83 words
A semiconductor memory device as claimed in claim 3, wherein said selection circuit includes a write mask decoder which decodes address signals supplied from the outside at the time of said one-bit input and output mode configuration, and a selector which sends said activated output to said write amplifier enable signal line at the time of said one-bit input and output mode configuration and sends a write mask data from said receiving means, as they are, to said write amplifier enable signal lines.
Claim 7
Dependent Claim
123 words
In a memory write mask system for a semiconductor memory device which can be used by switching in one-bit input and output mode and in multi-bit input and output mode by sharing the use of a pellet, the memory write mask system comprising the steps of: connecting, to each of the write amplifiers for executing data write to a memory cell array, a write data line for transmitting a write data and a write amplifier enable signal line for controlling the activation of said write amplifier; and inputting a write mask data for designating a write mask for every bit to said write amplifiers by means of said write amplifier enable signal lines at the time of multi-bit input and output mode configuration.
Claim 8
Dependent Claim
123 words
In a memory write mask system for a semiconductor memory device which can be used by switching in one-bit input and output mode and in multi-bit input and output mode by sharing the use of a pellet, the memory write mask system comprising the steps of: connecting, to each of the write amplifiers for executing data write to a memory cell array, a write data line for transmitting a write data and a write amplifier enable signal line for controlling the activation of said write amplifier; and inputting a write mask data for designating a write mask for every bit to said write amplifiers by means of said write amplifier enable signal lines at the time of multi-bit input and output mode configuration.
Claim 9
Dependent Claim
107 words
A memory write mask system as claimed in claim 6, wherein a write mask data is obtained on said write amplifier enable signal lines via a selection circuit which outputs pieces of binary information equal in number to that of said write amplifier enable signal lines in response to a control signal which designates the difference between said one-bit input and output mode configuration and said multi-bit input and output mode configuration, address signals which designate one of said write amplifier enable signal lines at the time of said one-bit input and output mode configuration, and a write mask data which is input to said input terminal.
Claim 10
Dependent Claim
71 words
A memory write mask system as claimed in claim 6, wherein said selection circuit is constructed by a write mask decoder which activates one of said write amplifier enable signal lines by decoding said address signals at the time of said one-bit input and output mode configuration, and outputs a write mask data input from said input terminal, as it is, at the time of multi-bit input and output mode configuration.
Claim 11
Dependent Claim
91 words
A memory write mask system as claimed in claim 7, wherein said selector circuit is constructed by a write mask decoder which activates one of the outputs by decoding said address signals only at the time of one-bit input and output mode configuration, and a selector which respectively sends said output at the time of one-bit input and output mode configuration, and a write mask data input from said input terminal at the time of multi-bit input and output mode configuration, as they are, to said write amplifier enable signal lines.
References Cited (Backward Citations)
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