EP0385136A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Microprocessor cooperating with a coprocessor
Assignee: NEC Corp
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Filing: 1990-02-05
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Granted: —
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Expires: 2010-02-05
Abstract
Abstract A microprocessor, which can be coupled externally with a coprocessor in order to extend an instruction set, includes a first set of terminals to be coupled to the coprocessor for data transfer between the microprocessor and the coprocessor, and a second set of terminals to be coupled to an external memory other than the coprocessor for data transfer between the microprocessor and the external memory. The microprocessor also includes a first but control unit connected to the first set of terminals for controlling the first set of terminals, independently of the second set of terminals, thereby to control the data transfer between the microprocessor and the coprocessor, and a second but control unit connected to the second set of terminals for controlling the second set of terminals, independently of the first set of terminals, thereby to control the data transfer between the microprocessor and the external memory.
Inventors
- 👤 Hiroaki C/O Nec Corporation Kaneko
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 07:35
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3877; G06F9/3885
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
139 words
A microprocessor to be coupled externally with a coprocessor in order to extend an instruction set, including a first set of terminals to be coupled to the coprocessor for data transfer between the microprocessor and the coprocessor, a second set of terminals to be coupled to an external device other than the coprocessor for data transfer between the microprocessor and the external device, a first control means connected to the first set of terminals for controlling the first set of terminals, independently of the second set of terminals, thereby to control the data transfer between the microprocessor and the coprocessor, and a second control means connected to the second set of terminals for controlling the second set of terminals, independently of the first set of terminals, thereby to control the data transfer between the microprocessor and the external device.
Claim 2
Dependent Claim
139 words
A microprocessor to be coupled externally with a coprocessor in order to extend an instruction set, including a first set of terminals to be coupled to the coprocessor for data transfer between the microprocessor and the coprocessor, a second set of terminals to be coupled to an external device other than the coprocessor for data transfer between the microprocessor and the external device, a first control means connected to the first set of terminals for controlling the first set of terminals, independently of the second set of terminals, thereby to control the data transfer between the microprocessor and the coprocessor, and a second control means connected to the second set of terminals for controlling the second set of terminals, independently of the first set of terminals, thereby to control the data transfer between the microprocessor and the external device.
Claim 3
Dependent Claim
161 words
A microprocessor claimed in Claim 1 wherein the microprocessor also includes an instruction decoder coupled to the second control means so as to decode an instrucion fetched by the second control means, and an exeuction unit coupled to receive the instruction decoded by the instruction decoder and controls the first and second control means an the basis of the received decoded instruction in such a manner that when an operation is to be executed by the coprocessor, the second control means fetches, from the external device through the second set of terminals, data required for the operation to be executed by the coprocessor, and the fetched data is transferred through the second Set of terminals to the coprocessor under control of the first control means, and after the operation has been executed by the coprocessor, the result of the operation is transferred from the coprocessor to the first control means and then through the second control means to the external device.
Claim 4
Dependent Claim
171 words
A microprocessor system comprising: a memory; a coprocessor; and a microprocessor having a first bus cycle control unit coupled to the memory through a system bus for data transfer between the microprocessor and the memory, and a second bus cycle control unit independently of the first bus cycle control unit and coupled to the coprocessor through a coprocessor bus independently of the system bus, for data transfer between the microprocessor and the coprocessor, whereby when an operation is executed by the coprocessor, the first bus cycle control unit fetches, from the memory through the system bus, date required for the operation to be executed by the coprocessor, and the fetched data is transferred through the second bus cycle control unit to the coprocessor under control of the bus cycle control unit, and after the operation has been executed by the coprocessor, the result of the operation is transferred from the coprocessor to the second bus cycle control unit and then returned through the first bus cycle control unit to the memory.
Claim 5
Dependent Claim
171 words
A microprocessor system comprising: a memory; a coprocessor; and a microprocessor having a first bus cycle control unit coupled to the memory through a system bus for data transfer between the microprocessor and the memory, and a second bus cycle control unit independently of the first bus cycle control unit and coupled to the coprocessor through a coprocessor bus independently of the system bus, for data transfer between the microprocessor and the coprocessor, whereby when an operation is executed by the coprocessor, the first bus cycle control unit fetches, from the memory through the system bus, date required for the operation to be executed by the coprocessor, and the fetched data is transferred through the second bus cycle control unit to the coprocessor under control of the bus cycle control unit, and after the operation has been executed by the coprocessor, the result of the operation is transferred from the coprocessor to the second bus cycle control unit and then returned through the first bus cycle control unit to the memory.
Claim 6
Dependent Claim
42 words
A microprocessor system as claimed in Claim 3 further including a second coprocessor coupled to the coprocessor bus to the microprocessor so that the first mentioned coprocessor and the second coprocessor can execute an operation assigned thereto independently of the other coprocessor.
References Cited (Backward Citations)
No citation records indexed.
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