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EP0383549A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Ring oscillator

Assignee: ICT INTERNATIONAL CMOS Tech Inc
•
Filing: 1990-02-13
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Granted: —
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Expires: 2010-02-13
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Abstract

Abstract A CMOS ring oscillator includes an odd number of serially connected inverter stages with each stage comprising a CMOS transistor pair (26, 28). The output of each stage is taken at the common terminal of the CMOS transistor pair (26, 28) with capacitive means (30) shunting the output of each stage to circuit ground. The input of each stage is applied at the gate of the p-channel transistor (26). A fixed reference voltage, V REF , is applied to the gate of each n-channel transistor (28), whereby the discharge of voltage on the capacitive means (30) through the n-channel transistor (28) is independent of supply voltage.

Inventors

  • 👤 Dhaval J. Brahmbhatt
  • 👤 Mehrdad Mofidi (Nmi)

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-02 15:52
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/03; H03K3/0315; H03K3/353; H03K3/354

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 122 words
A ring oscillator comprising an odd number of serially connected inverter stages, each stage including a p-channel transistor (26) serially connected with an n-channel transistor (28) between a first voltage potential (V CC ) and a second voltage potential and with the common terminal of the serially connected transistors (26, 28) being an output, means connecting the output of one stage with the gate terminal of the p-channel transistor (26) in the succeeding stage, and capacitive means (30) connected to each output, characterised by a reference voltage (V REF ) connected to the gate of each n-channel transistor (28) whereby the discharge of the capacitive means (30) of a preceding stage is relatively independent of the first voltage potential (V CC ).
Claim 2
Dependent Claim 122 words
A ring oscillator comprising an odd number of serially connected inverter stages, each stage including a p-channel transistor (26) serially connected with an n-channel transistor (28) between a first voltage potential (V CC ) and a second voltage potential and with the common terminal of the serially connected transistors (26, 28) being an output, means connecting the output of one stage with the gate terminal of the p-channel transistor (26) in the succeeding stage, and capacitive means (30) connected to each output, characterised by a reference voltage (V REF ) connected to the gate of each n-channel transistor (28) whereby the discharge of the capacitive means (30) of a preceding stage is relatively independent of the first voltage potential (V CC ).
Claim 3
Dependent Claim 27 words
A ring oscillator as claimed in Claim 1, characterised in that said capacitive means (30) comprises a capacitor connected between each output and the second voltage potential.
Claim 4
Dependent Claim 25 words
A ring oscillator as claimed in Claim 1, characterised in that said capacitive means (30) comprises the gate structure of the succeeding p-channel transistor (26).
Claim 5
Dependent Claim 31 words
A ring oscillator as claimed in any preceding claim, characterised in that the width-to-length ratio of each p-channel transistor (26) is greater than the width-to-length ratio of each n-channel transistor (28).
Claim 6
Dependent Claim 18 words
A ring oscillator as claimed in any preceding claims, characterised in that the second voltage potential is ground.

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