EP0381469A2
Expired / Lapsed
EP
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Method and data processing unit for pipeline processing of register and register modifying specifiers within the same instruction
Assignee: Digital Equipment Corp
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Filing: 1990-01-31
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Granted: —
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Expires: 2010-01-31
Abstract
Abstract In a pipeline processor, simultaneous decoding of multiple specifiers in a variable-length instruction causes a peculiar problem of an intra-instruction read conflict that occurs whenever an instruction includes an autoincrement or an autodecrement specifier which references either directly or indirectly a register specified by a previously occurring specifier for the current instruction. To avoid stalls during the preprocessing of instructions by the instruction unit, register pointers rather than register data are usually passed to the execution unit because register data is not always available at the time of instruction decoding. If an intra-instruction read conflict exists, however, the operand value specified by the conflicting register specifier is the initial value of the register being incremented or decremented, and this initial value will have been changed by the time that the execution unit executes the instruction. Preferably, the proper initial value is obtained prior to the incrementing or decrementing of the conflicting register by putting the instruction decoder into a special IRC mode in which only one specifier is decoded per cycle, and if a specifier being decoded is a register specifier, the content of the specified register is transmitted to the execution unit. Circuitry for detecting an intra-instruction read conflict is disclosed as well as an efficient method for handling interrupts, exceptions and flushes that may occur during the processing of an instruction having an intra-instruction read conflict.
Inventors
- 👤 David B. Fite
- 👤 Mark A. Firstenberg
- 👤 Lawrence O. Herman
- 👤 John E. Murray
- 👤 Ronald M. Salett
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 16:00
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30145; G06F9/3016; G06F9/30167; G06F9/30149; G06F9/30163; G06F9/3017; G06F9/30178; G06F9/38; G06F9/3802; G06F9/3816; G06F9/3818; G06F9/3822; G06F9/3824; G06F9/3861; G06F9/3863
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
123 words
A method of preprocessing, after decoding for execution in a pipelined processor, instructions having an operation code, a first register specifier and a following second specifier, the method comprising: detecting whether for each of the instructions the preprocessing of the second specifier changes the value of the register specified by the first register specifier; decoding the specifiers sequentially for instructions in which the detecting indicates that the preprocessing of the second specifier modifies the value of the register specified by the first register specifier; and decoding the first register specifier and the second specifier simultaneously for instructions in which the detecting indicates that the preprocessing of the second specifier does not modify the value of the register specified by the first register specifier.
Claim 2
Independent Claim
123 words
A method of preprocessing, after decoding for execution in a pipelined processor, instructions having an operation code, a first register specifier and a following second specifier, the method comprising: detecting whether for each of the instructions the preprocessing of the second specifier changes the value of the register specified by the first register specifier; decoding the specifiers sequentially for instructions in which the detecting indicates that the preprocessing of the second specifier modifies the value of the register specified by the first register specifier; and decoding the first register specifier and the second specifier simultaneously for instructions in which the detecting indicates that the preprocessing of the second specifier does not modify the value of the register specified by the first register specifier.
Claim 3
Dependent Claim
41 words
A method as claimed in Claim 1, further comprising passing register pointers to an execution unit (13) for the register specifiers that are decoded simultaneously, and passing register values to the execution unit for the register specifiers that are decoded sequentially.
Claim 4
Dependent Claim
119 words
A method as claimed in Claim 1 or 2, including maintaining, during instruction decoding and execution, a first set of values for a plurality of registers (651) in an instruction decoding unit and a second set of values for the registers (652) in the instruction execution unit: for instructions in which the detecting indicates that the preprocessing of the second specifier modifies the value of only those registers different from the register specified by the first register specifier, decoding the first register specifier and the second specifier simultaneously; and for instructions in which the detecting indicates that the preprocessing of the second specifier modifies the value of the register specified by the first register specifier, decoding the specifiers sequentially.
Claim 5
Dependent Claim
59 words
A method as claimed in Claim 3, further comprising inhibiting the decoding of instructions following the instructions in which the detecting indicates that the preprocessing of the second specifier modifies the value of the register specified by the first register specifier, the inhibition being maintained until the value of the specified register in the instruction execution unit is modified.
Claim 6
Dependent Claim
39 words
A method as claimed in Claim 3 or 4, further comprising returning the register values in the instruction decoding unit to the initial unmodified values by replacing their values with the respective register values in the instruction execution unit.
Claim 7
Dependent Claim
54 words
A method as claimed in Claim 3, 4 or 5, further comprising passing register pointers from the instruction decoding unit to the execution unit for the register specifiers that are decoded simultaneously, and passing register values from the instruction decoding unit to the instruction execution unit for the register specifiers that are decoded sequentially.
Claim 8
Independent Claim
111 words
A method as claimed in any of Claims 3 to 6, further comprising modifying the register values specified by the second specifier in both the instruction decoding unit and the instruction execution unit prior to execution of the instruction including the first and second specifiers when the specifiers in the instruction are decoded simultaneously; and modifying the specified register value in the instruction decoding unit prior to execution of the instruction including the first and second specifiers, and modifying the value of the specified register in the instruction execution unit after execution of the instruction included in the first and second specifiers when the specifiers in the instruction are decoded sequentially.
Claim 9
Dependent Claim
129 words
A dataprocessing unit for a pipelined processor for preprocessing, for execution, instructions having an operation code, a first register specifier and a following second specifier, comprising means (110) for detecting whether for each of the instructions the preprocessing of the second specifier changes the value of the register specified by the first register specifier, means (20) for decoding the specifiers sequentially for instructions in which the detecting indicates that the preprocessing of the second specifier modifies the value of the register specified by the first register specifier, and means (20) for decoding the first register specifier and the second specifier simultaneously for instructions in which the detecting indicates that the preprocessing of the second specifier does not modify the value of the register specified by the first register specifier.
Claim 10
Dependent Claim
129 words
A dataprocessing unit for a pipelined processor for preprocessing, for execution, instructions having an operation code, a first register specifier and a following second specifier, comprising means (110) for detecting whether for each of the instructions the preprocessing of the second specifier changes the value of the register specified by the first register specifier, means (20) for decoding the specifiers sequentially for instructions in which the detecting indicates that the preprocessing of the second specifier modifies the value of the register specified by the first register specifier, and means (20) for decoding the first register specifier and the second specifier simultaneously for instructions in which the detecting indicates that the preprocessing of the second specifier does not modify the value of the register specified by the first register specifier.
Claim 11
Dependent Claim
43 words
A dataprocessing unit as claimed in Claim 8, further comprising means for passing register pointers to execution means (13) for the register specifiers that are decoded simultaneously, and passing register values to the execution means for the register specifiers that are decoded sequentially.
Claim 12
Dependent Claim
38 words
A unit as claimed in Claim 8 or 9, including means (118) for inhibiting the decoding of instructions following detection indicating modification of the value of the register specified by the first register specifier by the detecting means.
Claim 13
Dependent Claim
43 words
11 A pipeline processor comprising an instruction decoding unit (12), a processing unit as claimed in any of Claims 8 to 10 and an execution unit (13) for processing instructions having an operation code, a first register specifier and a following second specifier.
Claim 14
Dependent Claim
38 words
A processor as claimed in Claim 11, including means for returning the register values in the instruction decoding unit to the unmodified values by replacing their values with those from the respective values in the instruction execution unit.
Claim 15
Dependent Claim
53 words
A processor as claimed in 11 or 12, including means for passing register pointers from the instruction decoding unit to the execution unit for the register specifiers that are decoded simultaneously, and for passing register values from the instruction decoding unit to the execution unit for the register specifiers that are decoded sequentially.
Claim 16
Dependent Claim
93 words
A processor as claimed in Claim 11, 12 or 13, including means for modifying the register values specified by the second specifier in both the instruction decoding unit and the execution unit prior to execution of the instruction including the first and second specifiers, and means for modifying the specified register value in the instruction decoding unit prior to execution of the instruction including the first and second specifiers and for modifying the value of the specified register in the execution unit after execution of the instruction including the first and second specifiers.
References Cited (Backward Citations)
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