EP0381325A2
Expired / Lapsed
EP
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Synchronising and processing of memory access operations
Assignee: Digital Equipment Corp
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Filing: 1990-01-12
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Granted: —
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Expires: 2010-01-12
Abstract
Abstract A synchronising scheme for processing "locked" memory access requests from various computer system units is provided by a System Control Unit (SCU) (14). The SCU is provided with a directory of lock bits in such a way that each memory address associated with a memory access request is mapped to a corresponding location in the lock directory. Incoming requests for a given memory location are processed by interrogating the corresponding lock bit in the lock directory. If the lock bit is not set, the request is granted. The lock bit is subsequently set and maintained in that state until the unit requesting the lock has completed its memory access operation and sends an "unlock" request. If the interrogated lock bit is found to be set, the lock request is denied and the requesting port is notified of the denial and requested to try again. Fairness is incorporated in the processing of denied lock requests by means of a reserve list onto which denied requests are sequentially positioned on a first-come-first-served basis.
Inventors
- 👤 Scott Arnold
- 👤 James Kann
- 👤 Stephen J. Delahunt
- 👤 Trygve Fossum
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 09:30
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/52
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
101 words
A method of processing locked memory access requests in a multiprocessor computer system comprising: storing a directory of lock bits, each lock bit corresponding to a predefined segment of memory locations, the status of each of the lock bits representing whether or not the corresponding memory segment is locked; ascertaining, for each lock request being processed, whether or not the lock bit corresponding to the memory segment containing the memory location being addressed by the request is set; and granting the request if the corresponding lock bit is not set, and denying the request if the corresponding lock bit is set.
Claim 2
Independent Claim
101 words
A method of processing locked memory access requests in a multiprocessor computer system comprising: storing a directory of lock bits, each lock bit corresponding to a predefined segment of memory locations, the status of each of the lock bits representing whether or not the corresponding memory segment is locked; ascertaining, for each lock request being processed, whether or not the lock bit corresponding to the memory segment containing the memory location being addressed by the request is set; and granting the request if the corresponding lock bit is not set, and denying the request if the corresponding lock bit is set.
Claim 3
Dependent Claim
36 words
A method of processing locked memory access requests as claimed in Claim 1 in which all requests for access to memory locations within the same segment are mapped to the same lock bit in the directory.
Claim 4
Dependent Claim
45 words
A method of processing locked memory access requests as claimed in Claim 1 or Claim 2 in which each request which is denied is stored on a reserve list, unless the list is full or the request has already been so stored, in sequential order.
Claim 5
Dependent Claim
43 words
A method of processing locked memory access requests as claimed in Claim 3 in which the oldest request on the reserve list is granted when the lock bit which originally resulted in the said request being denied is substantially found to be unset.
Claim 6
Dependent Claim
137 words
A multiprocessor computer system including a system control unit (SCU) (14) for operating a plurality of central processor units (CPUs) (12) in a parallel fashion with at least one input/output (I/O) interface (20), the system being characterised by means (100) for storing within the SCU (14) a directory of lock bits, each lock bit corresponding to a predefined segment of memory locations, the status of each of the lock bits representing whether or not the corresponding memory segment is locked; means for determining, for each lock request being processed, whether or not the lock bit corresponding to the memory segment containing the memory location being addressed by the request is set; and means for granting the request if the corresponding lock bit is not set and for denying the request if the corresponding lock bit is set.
Claim 7
Dependent Claim
137 words
A multiprocessor computer system including a system control unit (SCU) (14) for operating a plurality of central processor units (CPUs) (12) in a parallel fashion with at least one input/output (I/O) interface (20), the system being characterised by means (100) for storing within the SCU (14) a directory of lock bits, each lock bit corresponding to a predefined segment of memory locations, the status of each of the lock bits representing whether or not the corresponding memory segment is locked; means for determining, for each lock request being processed, whether or not the lock bit corresponding to the memory segment containing the memory location being addressed by the request is set; and means for granting the request if the corresponding lock bit is not set and for denying the request if the corresponding lock bit is set.
Claim 8
Dependent Claim
57 words
A multiprocessor computer system as claimed in Claim 5 in which each of the lock bits in the lock directory corresponds to a block of memory defined by a CPU cache, all memory addresses which are associated with a memory access request and which fall within a particular cache block being mapped to the same lock bit.
Claim 9
Dependent Claim
53 words
A multiprocessor computer system as claimed in any one of Claims 5 to 6 including means for defining a reserve list of denied requests, and means for storing each request which is denied on the reserve list, unless the list is full or the request has already been so stored, in sequential order.
Claim 10
Dependent Claim
39 words
A multiprocessor computer system as claimed in Claim 7 including means for granting the oldest request on the reserve list when the lock bit which originally resulted in the said request being denied is substantially found to be unset.
Claim 11
Dependent Claim
38 words
A multiprocessor computer system as claimed in Claim 7 or Claim 8 including overide means adapted to advance a request in the reserve list, other than the oldest request, when an overide condition exists for the said request.
References Cited (Backward Citations)
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