EP0381064A2
Expired / Lapsed
EP
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Addressing mechanism for accessing multiple neighboring locations from full field memory in parallel
Assignee: Honeywell Inc
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Filing: 1990-01-26
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Granted: —
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Expires: 2010-01-26
Abstract
Abstract An apparatus for accessing a plurality of neighboring pixel locations from a full field memory (30) in parallel includes means for dividing the full field memory into quarters (14, 16, 18, 20), means (10, 12) for modifying incoming X and Y addresses to access the screen location which is contained in its addressing space, and means (22) for arranging the data buses so as to cause the pixels to be output on the appropriate screen location positions, as, for example, the four corners (I0, I1, I2, I3) of a portion of a display screen.
Inventors
- 👤 William R. Hancock
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 23:38
CPC Classifications
G; G06; G06T; G06T1/00; G06T1/60
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
104 words
An apparatus for accessing four neighboring pixel locations from a full field memory in a video readout system in parallel, characterized by : a) means (30) for dividing the full field memory into quarters (14, 16, 18, 20) wherein each quarter has an address and data bus; b) means (10, 12) for modifying X and Y addresses read into or accessed from the full field memory so as to access the corner which is contained in its addressing space; and c) means (22) for arranging the address and data buses so as to cause the four pixels to be output on appropriate corner positions.
Claim 2
Independent Claim
104 words
An apparatus for accessing four neighboring pixel locations from a full field memory in a video readout system in parallel, characterized by : a) means (30) for dividing the full field memory into quarters (14, 16, 18, 20) wherein each quarter has an address and data bus; b) means (10, 12) for modifying X and Y addresses read into or accessed from the full field memory so as to access the corner which is contained in its addressing space; and c) means (22) for arranging the address and data buses so as to cause the four pixels to be output on appropriate corner positions.
Claim 3
Dependent Claim
35 words
The apparatus of Claim 1, characterized in that the data buses are arranged according to a multiplexing scheme (40, 42, 44, 46) based upon the values of the least significant bits of X and Y.
Claim 4
Dependent Claim
39 words
The apparatus of Claim 1 or 2, characterized in that the full field memory dividing means (30) comprises four random access memory devices (14, 16, 18, 20), each of which stores a quarter of the total data in memory.
Claim 5
Dependent Claim
200 words
The apparatus according to claim 3 for accessing four neighboring pixel locations having coordinate addresses in parallel, characterized by: a) the full field memory (30) comprising first, second, third and fourth random access memory devices (14, 16, 18, 20) having inputs to receive address information and data and bidirectional buses (DATA0 - DATA3) to provide access to stored data; b) first and second address control chips (10, 12), each control chip including a means for counting bits, a means for multiplexing data and a means for detecting overflow of data, the first and second address control chips having buses connected to the first through fourth memory means so as to cause the pixel locations to be routed to designated random access memory devices as designated by the least significant bits of the coordinate addresses of the pixel locations; and c) a data control chip (22) connected to the bidirectional buses (DATA0 - DATA3) of the first through fourth random access memory devices and further having bidirectional data bus drivers connected to the random access devices' bidirectional buses (DATA0 - DATA3), means for detecting zero overflow and blanking pixels being routed to the outputs, and further including means for multiplexing data.
Claim 6
Dependent Claim
44 words
The apparatus of Claim 4, characterized in that the data control chip (22) includes four outputs (I0, I1, I2, I3) corresponding to screen locations in the upper left corner, upper right corner, lower left corner and lower right corner of a display screen, respectively.
Claim 7
Dependent Claim
50 words
The apparatus of Claim 4 or 5, characterized in that the data control chip (22) further has a means for receiving video data and means for busing (DATA0 - DATA3) the video data to the first, second, third and fourth random access memory devices (14, 16, 18, 20) for storage.
Claim 8
Independent Claim
127 words
An apparatus for accessing a plurality of neighboring pixel locations from a full field memory (30) in parallel for use in a video readout system having a display screen with screen locations for displaying pixel information, characterized by : a) means for dividing the full field memory into sections (14, 16, 18, 20) wherein each section has an address and data bus; b) means (10, 12) for modifying X and Y addresses read into or accessed from the full field memory so as to access the screen location which is contained in its addressing space; and c) means (22) for arranging the address and data buses so as to cause the plurality of pixels to be output according to a predetermined arrangement according to its screen location.
Claim 9
Independent Claim
127 words
An apparatus for accessing a plurality of neighboring pixel locations from a full field memory (30) in parallel for use in a video readout system having a display screen with screen locations for displaying pixel information, characterized by : a) means for dividing the full field memory into sections (14, 16, 18, 20) wherein each section has an address and data bus; b) means (10, 12) for modifying X and Y addresses read into or accessed from the full field memory so as to access the screen location which is contained in its addressing space; and c) means (22) for arranging the address and data buses so as to cause the plurality of pixels to be output according to a predetermined arrangement according to its screen location.
Claim 10
Dependent Claim
37 words
The apparatus of Claim 7, characterized in that the address and data buses are controlled according to a multiplexing scheme (40, 42, 44, 46) based upon the values of the least significant bits of X and Y.
Claim 11
Dependent Claim
46 words
The apparatus of Claim 4 or 7, characterized in that the plurality of neighboring pixels includes a matrix of pixels and the apparatus is layered so as to be adapted to access or write a matrix which is larger than a two-by-two matrix of neighboring pixels.
Claim 12
Dependent Claim
14 words
The apparatus of Claim 8, characterized in that the matrix is a four-by-four matrix.
Claim 13
Independent Claim
33 words
The apparatus according to one of the preceding claims, characterized in that the least significant bits of X and Y are interleaved within the quarters or sections, respectively, of the full field memory.
Claim 14
Independent Claim
19 words
The apparatus of one of the preceding claims, characterized in that the elements are doubled into a PING/PONG scheme.
Claim 15
Independent Claim
117 words
An apparatus for writing a plurality of neighboring pixel locations into a full field memory (30) in parallel for use in a video redout system having a display screen with screen locations for displaying pixel information comprising: a) means for dividing the full field memory into sections (14, 16, 18, 20) wherein each section has an address and data bus; and b) means (10, 12) for assigning X and Y addresses written into the full field memory so as to correspond to the screen location which is contained in the full field memory's addressing space according to a multiplexing scheme (40, 42, 44, 46) based upon the values of the least significant bits of X and Y.
Claim 16
Independent Claim
117 words
An apparatus for writing a plurality of neighboring pixel locations into a full field memory (30) in parallel for use in a video redout system having a display screen with screen locations for displaying pixel information comprising: a) means for dividing the full field memory into sections (14, 16, 18, 20) wherein each section has an address and data bus; and b) means (10, 12) for assigning X and Y addresses written into the full field memory so as to correspond to the screen location which is contained in the full field memory's addressing space according to a multiplexing scheme (40, 42, 44, 46) based upon the values of the least significant bits of X and Y.
Claim 17
Dependent Claim
16 words
The apparatus of Claim 13, wherein the plurality of neighboring pixels includes at least four pixels.
References Cited (Backward Citations)
No citation records indexed.
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