EP0380861A2
Expired / Lapsed
EP
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Improved data consistency between cache memories and the main memory in a multi-processor computer system
Assignee: Digital Equipment Corp
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Filing: 1989-09-28
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Granted: —
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Expires: 2009-09-28
Abstract
Abstract A method for insuring data consistency between a plurality of individual processor cache memories and the main memory in a multi-processor cache memories and the main memory in a multi-processor computer system is provided which is capable of (1) detecting when one of a set of predefined data inconsistency states occurs as a data transaction request is being processed, and (2) correcting the data inconsistency states so that the operation may be executed in a correct and consistent manner. I particular, the method is adapted to address two kinds of data inconsistency states: (1) A request for a operation from a system unit to main memory when the location to be written to is present in the cache of some processor unit-in such a case, data in the cache is "state" and the data inconsistency is avoided by preventing the associated processor from using the "stale" data; and (2) when a read operation is requested of main memory by a system unit and the location to be read may be written or has already been written in the cache of some processor - in this case, the data in main memory is "stale" and the data inconsistency is avoided by insuring that the data returned to the requesting unit is the updated data in the cache. The presence of one of the above-described data inconsistency states is detected in a SCU-based multi-processing system by providing the SCU with means for maintaining a copy of the cache directories for each of the processor caches. The SCU continually compares address data accompanying memory access requests with what is stored in the SCU cache directories in order to determine the presence of predefined conditions indicative of data inconsistencies, and subsequently executes corresponding predefined fix-up sequences.
Inventors
- 👤 David A. Webb, Jr.
- 👤 Michael E. Flynn
- 👤 Ricky C. Hetherington
- 👤 Tryggve Fossum
- 👤 Scott Arnold
- 👤 Stephen J. De La Hunt
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 16:07
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0817; G06F12/0822
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
147 words
Apparatus for ensuring data consistency between a plurality of CPU memories and a system memory in a multi-processor computer system, having a system control unit (SCU) for operating a plurality of central processor units (CPUs) in a parallel fashion in combination with at least one input/output (I/O) unit, wherein each of said CPUs and I/O units is ported into the SCU, the SCU being operative controllably to allow the CPUs and the I/O units to access addressed segments of a common system memory, and wherein each of the CPU memories is operable to store predefined memory locations from the system memory, the apparatus comprising means for detecting when one of a set of predefined data inconsistency states occurs as a memory transaction request is being processed, and means for correcting the data inconsistency state so that the memory transaction request may be executed without generating data inconsistencies.
Claim 2
Dependent Claim
147 words
Apparatus for ensuring data consistency between a plurality of CPU memories and a system memory in a multi-processor computer system, having a system control unit (SCU) for operating a plurality of central processor units (CPUs) in a parallel fashion in combination with at least one input/output (I/O) unit, wherein each of said CPUs and I/O units is ported into the SCU, the SCU being operative controllably to allow the CPUs and the I/O units to access addressed segments of a common system memory, and wherein each of the CPU memories is operable to store predefined memory locations from the system memory, the apparatus comprising means for detecting when one of a set of predefined data inconsistency states occurs as a memory transaction request is being processed, and means for correcting the data inconsistency state so that the memory transaction request may be executed without generating data inconsistencies.
Claim 3
Dependent Claim
92 words
Apparatus as claimed in claim 1 wherein the predefined data inconsistency states include: (1) a request for a memory write operation from one of the CPUs or the I/O units to a location within the system memory which is also present in the memory of one of the other CPUs; and (2) a request for a read operation on the system memory by one of the CPUs or I/O units, where the location to be read may be written or has been written in the memory of one of the other CPUs.
Claim 4
Dependent Claim
74 words
Apparatus as claimed in claim 2 wherein the first data inconsistency state is corrected by preventing the CPU whose memory contains the memory location for which the write operation is requested by the CPU or the I/O unit from using data stored therein; and wherein the second data inconsistency state is corrected by returning to the requesting CPU or I/O unit data that has been written in the memory of another of the CPUs.
Claim 5
Dependent Claim
114 words
Apparatus as claimed in claim 3 wherein the data inconsistency states are detected by means in the SCU for maintaining a copy of the memory directories for each of the memories for the CPUs, the directories containing the physical addresses of memory data in the memory locations and a status bit indicative of whether or not data has been written in the memories without the system memory having been updated, and wherein the SCU compares the address data accompanying a memory access request being processed with the information stored in the SCU directories in order to determine the presence of a data inconsistency state and the action required to correct the data inconsistency state.
Claim 6
Dependent Claim
15 words
Apparatus as claimed in any preceding claim wherein the CPU memory is a cache memory.
Claim 7
Dependent Claim
28 words
A multi-processor computer system including apparatus for ensuring data consistency between a plurality of associated CPU memories and the system main memory as claimed in any preceding claim.
Claim 8
Independent Claim
146 words
A method for ensuring data consistency between a plurality of central processor unit (CPU) memories and a system memory in a multi-processor system of the type having a system control unit (SCU) for operating the plurality of CPUs in a parallel fashion in combination with at least one input/output (I/O) unit, wherein each of the CPUs and I/O units is ported into the SCU, the SCU being operative controllably to allow the CPUs and the I/O units to access addressed segments of a common system memory, and wherein each of the CPU memories is operable to store predefined memory locations from the system memory; the method comprising: detecting when one of a set of predefined data inconsistency states occurs as a memory transaction request is being processed; and correcting the data inconsistency state so that the memory transaction request may be executed without generating data inconsistencies.
Claim 9
Independent Claim
146 words
A method for ensuring data consistency between a plurality of central processor unit (CPU) memories and a system memory in a multi-processor system of the type having a system control unit (SCU) for operating the plurality of CPUs in a parallel fashion in combination with at least one input/output (I/O) unit, wherein each of the CPUs and I/O units is ported into the SCU, the SCU being operative controllably to allow the CPUs and the I/O units to access addressed segments of a common system memory, and wherein each of the CPU memories is operable to store predefined memory locations from the system memory; the method comprising: detecting when one of a set of predefined data inconsistency states occurs as a memory transaction request is being processed; and correcting the data inconsistency state so that the memory transaction request may be executed without generating data inconsistencies.
Claim 10
Dependent Claim
93 words
A method as claimed in claim 7, wherein the predefined data inconsistency states include: (1) a request for a memory write operation from one of the CPUs or the I/O units to a location within the system memory which is also present in the memory of one of the other CPUs; and (2) a request for a read operation on the system memory by one of the CPUs or I/O units, where the location to be read may be written or has been written in the memory of one of the other CPUs.
Claim 11
Dependent Claim
75 words
A method as claimed in claim 8 wherein the first data inconsistency state is corrected by preventing the CPU whose memory contains the memory location for which the write operation is requested by the CPU or the I/O unit from using data stored therein; and wherein the second data inconsistency state is corrected by returning to the requesting CPU or I/O unit data that has been written in the memory of another of the CPUs.
Claim 12
Dependent Claim
109 words
A method as claimed in claim 9 wherein the data inconsistency states are detected by maintaining a copy of the memory directories for each of memories for the CPUs, the directories containing the physical addresses of memory data in the memory locations and a status bit indicative of whether or not data has been written in the memories without the system memory having been updated, and wherein the SCU compares the address data accompanying a memory access request being processed with the information stored in the SCU directories in order to determine the presence of a data inconsistency state and the action required to correct the data inconsistency state.
References Cited (Backward Citations)
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