EP0380850A2
Expired / Lapsed
EP
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Multiple instruction preprocessing
Assignee: Digital Equipment Corp
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Filing: 1989-09-07
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Granted: —
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Expires: 2009-09-07
Abstract
Abstract A method of preprocessing multiple instructions prior to execution in a digital computer, and of avoiding the preprocessing of an instruction to read a register prior to the modification of the contents of that register by a preceding instruction; the method being characterised by: generating a composite write mask having a bit set for each register whose contents are to be modified by at least one decoded but not-yet-executed instruction preceding the said instruction; and stalling the processing of the said instruction when a register to be read by the said instruction is a register corresponding to a bit set in the composite write mask. The method also extends to the avoiding of the preprocessing of an instruction to modify the contents of a register prior to the reading of that register by a preceding instruction.
Inventors
- 👤 David B. Fite
- 👤 John E. Murray
- 👤 Michael M. Mckeon
- 👤 Mark A. Firstenberg
- 👤 William R. Grundman
- 👤 David A. Webb
- 👤 Ronald M. Salett
- 👤 Tryggve Fossum
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 19:09
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F9/355; G06F9/345; G06F9/38; G06F9/3836; G06F9/3838; G06F9/3854; G06F9/3858
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
105 words
A method of preprocessing multiple instructions prior to execution in a digital computer, and of avoiding the preprocessing of an instruction to read a register prior to the modification of the contents of that register by a preceding instruction; the method being characterised by: generating a composite write mask having a bit set for each register whose contents are to be modified by at least one decoded but not-yet-executed instruction preceding the said instruction; and stalling the processing of the said instruction when a register to be read by the said instruction is a register corresponding to a bit set in the composite write mask.
Claim 2
Independent Claim
105 words
A method of preprocessing multiple instructions prior to execution in a digital computer, and of avoiding the preprocessing of an instruction to read a register prior to the modification of the contents of that register by a preceding instruction; the method being characterised by: generating a composite write mask having a bit set for each register whose contents are to be modified by at least one decoded but not-yet-executed instruction preceding the said instruction; and stalling the processing of the said instruction when a register to be read by the said instruction is a register corresponding to a bit set in the composite write mask.
Claim 3
Independent Claim
105 words
A method of preprocessing multiple instructions prior to execution in a digital computer, and of avoiding the preprocessing of an instruction to modify the contents of a register prior to the reading of that register by a preceding instruction; the method being characterised by: generating a composite read mask having a bit set for each register to be read by at least one decoded but not-yet-executed instruction preceding the said instruction; and stalling the processing of the said instruction when a register whose contents are to be modified by the said instruction is a register corresponding to a bit set in the composite read mask.
Claim 4
Independent Claim
105 words
A method of preprocessing multiple instructions prior to execution in a digital computer, and of avoiding the preprocessing of an instruction to modify the contents of a register prior to the reading of that register by a preceding instruction; the method being characterised by: generating a composite read mask having a bit set for each register to be read by at least one decoded but not-yet-executed instruction preceding the said instruction; and stalling the processing of the said instruction when a register whose contents are to be modified by the said instruction is a register corresponding to a bit set in the composite read mask.
Claim 5
Dependent Claim
34 words
A method as claimed in Claim 1 or Claim 2 including updating the write or read mask each time the execution of an instruction is completed, and each time a new instruction is decoded.
Claim 6
Independent Claim
43 words
A method as claimed in any one of the preceding claims including resuming the preprocessing of the said instruction when the read or write mask no longer has a bit set for any register to be modified or read by the said instruction.
Claim 7
Independent Claim
65 words
A method as claimed in any one of the preceding claims in which the read or write mask is generated by producing a mask for each instruction that is decoded, queuing the masks for a plurality of decoded instructions in a mask queue until the execution of those instructions is completed, and combining all the queued masks to generate the composite read or write masks.
Claim 8
Dependent Claim
32 words
A method as claimed in Claim 5 in which the read or write mask for each instruction is removed from the mask queue when the execution of that instruction has been completed.
Claim 9
Dependent Claim
25 words
A method as claimed in Claim 5 or Claim 6 in which the decoding of new instructions is stalled whenever the mask queue is full.
Claim 10
Dependent Claim
35 words
A method as claimed in Claim 5 or Claim 6 or Claim 7 in which a selected number of read or write masks are retained in the mask queue in response to a flush signal.
Claim 11
Independent Claim
38 words
A method as claimed in any one of Claims 5 to 8 in which the mask queue includes multiple registers, and the read or write masks for successive instructions are stored in successive registers in the mask queue.
Claim 12
Dependent Claim
41 words
A method as claimed in Claim 9 including generating an insert pointer identifying the register which is to receive each new read or write mask in the mask queue, and incrementing the insert pointer each time a new instruction is decoded.
Claim 13
Dependent Claim
53 words
A method as claimed in Claim 9 or Claim 10 including generating a size signal identifying the number of read or write masks stored in the mask queue, incrementing the size signal each time a new instruction is decoded, and decrementing the size signal each time the execution of an instruction is completed.
Claim 14
Independent Claim
84 words
A method as claimed in any one of the preceding claims in which each instruction includes at least one source-operand specifier and at least one destination-operand specifier, and at least certain of the specifiers include register specifiers, the method further including comparing selected register specifiers in the said instruction with the composite read or write mask to determine when a register to be modified or read by the said instruction is a register having a bit set in said composite read or write mask.
Claim 15
Dependent Claim
47 words
A method as claimed in Claim 12 including holding a register specifier which produces an affirmative response in the comparing step, and continuing or repeating the comparison to determine when the affirmative response is cleared by removal of a read or write mask from the mask queue.
Claim 16
Independent Claim
54 words
A method as claimed in any one of the preceding claims for use with a computer having n general purpose registers comprising converting a general-purpose-register specifier for each general purpose register to be read by an instruction to a set bit on one of n lines corresponding respectively to the n general purpose registers.
References Cited (Backward Citations)
No citation records indexed.
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