EP0380849A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Preprocessing implied specifiers in a pipelined processor
Assignee: Digital Equipment Corp
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Filing: 1989-09-05
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Granted: —
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Expires: 2009-09-05
Abstract
Abstract An instruction decoder (20) generates implied specifiers for certain predefined instructions, and an operand processing unit (21) preprocesses most of the implied specifiers in the same fashion as express operand specifiers. For instructions having an implied autoincrement or autodecrement of the stack pointer, an implied read or write access type is assigned to the instruction and the decode logic is configured accordingly. Conflicts created by the implied specifiers are handled in the same manner as conflicts for express specifiers. Moreover, by using the same data paths for both the implied specifiers and the express specifiers, and by inserting queues between the instruction unit and the execution unit, performance gains are realised for instructions having implied specifiers as well as just express specifiers.
Inventors
- 👤 David B. Fite
- 👤 Mark A. Firstenberg
- 👤 John E. Murray
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 15:24
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/3005; G06F9/30054; G06F9/30145; G06F9/30149; G06F9/3016; G06F9/30163; G06F9/30167; G06F9/3017; G06F9/30178; G06F9/34; G06F9/38; G06F9/3802; G06F9/3816; G06F9/3818; G06F9/3822; G06F9/3824
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
69 words
A method of decoding an instruction in a pipelined processor, the instruction having an operation code, an express specifier appearing in the instruction and an implied specifier not explicitly appearing in the instruction but being implied from the operation code, the method being characterised by: receiving the operation code and the express specifier; and decoding the express specifier and generating the implied specifier in response to the operation code.
Claim 2
Independent Claim
69 words
A method of decoding an instruction in a pipelined processor, the instruction having an operation code, an express specifier appearing in the instruction and an implied specifier not explicitly appearing in the instruction but being implied from the operation code, the method being characterised by: receiving the operation code and the express specifier; and decoding the express specifier and generating the implied specifier in response to the operation code.
Claim 3
Dependent Claim
29 words
A method as claimed in Claim 1, wherein the express specifier is a register specifier and the implied specifier is an auto mode specifier for a stack pointer register.
Claim 4
Dependent Claim
31 words
A method as claimed in Claim 1 or Claim 2 further comprising the step of passing the decoded express specifier and the generated implied specifier together to an operand preprocessing unit.
Claim 5
Dependent Claim
33 words
A method as claimed in Claim 1 or Claim 2 or Claim 3 further comprising performing a conflict check for the implied specifier in substantially the same way as for the express specifier.
Claim 6
Independent Claim
40 words
A method as claimed in any one of the preceding claims including the step of storing operand information resulting from implied specifiers as well as express specifiers in a queue, and then passing the said information to an execution unit.
Claim 7
Dependent Claim
39 words
A method as claimed in Claim 5, wherein the operand information in the queue resulting from the decoding of the express operands is indistinguishable from the operand information in the queue resulting from the generation of the implied operands.
Claim 8
Independent Claim
178 words
A method of decoding multiple specifiers in a first variable length instruction having a first operation code defining operations upon operands, and express first, second and third specifiers appearing in the first instruction for providing information for locating operands for the first instruction including first and second source operands and a destination operand; and of decoding a second variable length instruction having a second operation code and an express fourth specifier appearing in the second instruction and an implied fifth specifier not explicitly appearing in the instruction but being implied from the second operation code; the express specifiers employing addressing modes independent of the operation code for providing the said information; the method being characterised by: receiving the first operation code and the first, second and third specifiers, and decoding the first, second and third specifiers to obtain the information for locating the first and second source operands and the destination operand; and receiving the second operation code and the fourth and fifth specifiers, decoding the fourth specifier and generating the fifth specifier from the second operation code.
Claim 9
Independent Claim
178 words
A method of decoding multiple specifiers in a first variable length instruction having a first operation code defining operations upon operands, and express first, second and third specifiers appearing in the first instruction for providing information for locating operands for the first instruction including first and second source operands and a destination operand; and of decoding a second variable length instruction having a second operation code and an express fourth specifier appearing in the second instruction and an implied fifth specifier not explicitly appearing in the instruction but being implied from the second operation code; the express specifiers employing addressing modes independent of the operation code for providing the said information; the method being characterised by: receiving the first operation code and the first, second and third specifiers, and decoding the first, second and third specifiers to obtain the information for locating the first and second source operands and the destination operand; and receiving the second operation code and the fourth and fifth specifiers, decoding the fourth specifier and generating the fifth specifier from the second operation code.
Claim 10
Dependent Claim
264 words
A data processing unit for processing variable length instructions having respective operation codes and respective sequences of multiple specifiers, the operation codes defining operations upon operands including source operands which are read during an operation and destination operands that are changed by an operation, the specifies providing information for locating the operands, the specifiers having operand addressing modes independent from the operation codes, the data processing unit being characterised by: a) instruction buffer means (19) for receiving an operation code and a respective sequence of multiple specifiers to be decoded; b) instruction decoding means (20) connected to the instruction buffer means (19) for decoding a first operand specifier in the respective sequence of multiple specifiers to obtain information for locating a first source operand, a second operand specifier in the respective sequence of multiple specifiers to obtain information for locating a second source operand, and a third operand specifier in the respective sequence of multiple specifiers to obtain information for locating a destination operand; c) operand fetching means (11) responsive to the information obtained by the instructions decoding means (20) for fetching the first and second operands; and d) execution means (13) for performing the operation indicated by the operation code received in the instruction buffer means (19) upon the source operands fetched by the operand fetching means (11) and changing the destination operand at the location specified by the information provided by the instruction decoding means (20); wherein the instruction decoding means (20) includes means responsive to the operation code for generating implied specifiers which do not appear explicitly in the said instructions.
Claim 11
Dependent Claim
264 words
A data processing unit for processing variable length instructions having respective operation codes and respective sequences of multiple specifiers, the operation codes defining operations upon operands including source operands which are read during an operation and destination operands that are changed by an operation, the specifies providing information for locating the operands, the specifiers having operand addressing modes independent from the operation codes, the data processing unit being characterised by: a) instruction buffer means (19) for receiving an operation code and a respective sequence of multiple specifiers to be decoded; b) instruction decoding means (20) connected to the instruction buffer means (19) for decoding a first operand specifier in the respective sequence of multiple specifiers to obtain information for locating a first source operand, a second operand specifier in the respective sequence of multiple specifiers to obtain information for locating a second source operand, and a third operand specifier in the respective sequence of multiple specifiers to obtain information for locating a destination operand; c) operand fetching means (11) responsive to the information obtained by the instructions decoding means (20) for fetching the first and second operands; and d) execution means (13) for performing the operation indicated by the operation code received in the instruction buffer means (19) upon the source operands fetched by the operand fetching means (11) and changing the destination operand at the location specified by the information provided by the instruction decoding means (20); wherein the instruction decoding means (20) includes means responsive to the operation code for generating implied specifiers which do not appear explicitly in the said instructions.
Claim 12
Dependent Claim
34 words
A data processing unit as claimed in Claim 8, wherein the means for generating the implied specifiers is capable of operating simultaneously with the decoding of express specifiers expressly appearing in the said instructions.
Claim 13
Dependent Claim
42 words
A data processing unit as claimed in Claim 8 or Claim 9 further comprising means for passing at least one decoded express specifier together with one generated implied specifier together to an operand preprocessing unit during each cycle of a system clock.
Claim 14
Dependent Claim
62 words
A data processing unit as claimed in Claim 8 or Claim 9 or Claim 10 including means for performing read and write conflict checks for the specifiers, the means for performing the said checks being operative in substantially the same way for both the express specifiers explicitly appearing in the instructions and the implied specifiers generated by the said means for generating.
Claim 15
Dependent Claim
83 words
A data processing unit as claimed in any one of Claims 8 to 11, further comprising a data path linking the operand fetching means (11) to the execution means (13) the data path including a queue for storing operand information resulting from the fetching of operands by the operand fetching means (11), and wherein the fetched operands include operands specified by implied specifiers generated by the decoder (20) as well as operands specified by express operand specifiers expressly appearing in the said instructions.
Claim 16
Dependent Claim
41 words
A data processing unit as claimed in Claim 12, wherein the operand information in the queue resulting from the decoding of the express operands is indistinguishable from the operand information in the queue resulting from the generation of the implied operands.
References Cited (Backward Citations)
No citation records indexed.
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