EP0380844A2 — Method and means for interfacing a system control…

Claim 1

Independent Claim 273 words

A multi-processing computer system comprising: of system units including a plurality of central processing units (CPUs) and at least one input/output (I/O) unit; a system memory for storage of data, said memory comprising at least one memory unit containing independently accessible memory segments; a system control unit (SCU) for operating said CPUs in a parallel fashion and allowing said CPUs and other system units to controllably access addressed segments of memory, said SCU being operative to accept memory commands from said system units, decode memory addresses accompanying said memory commands, and accommodate transfer of data to and from a system unit originating a memory command and corresponding addressed memory segments; and dedicated interface means for establishing communication between said SCU and said system memory, said interface means being linked on one end to said SCU and on the other end to a memory unit comprising said system memory, said interface means being adapted to allow memory commands received from said SCU to be controllably executed by accessing corresponding addressed segments in a memory unit and transferring data associated with said commands to and from said SCU and said corresponding addressed segments in a memory unit. 2. The multi-processing system of claim 1 wherein said interface means includes means for accepting and decoding memory commands and associated data from said SCU, means for regulating the transfer of decoded commands and corresponding memory addresses to corresponding ones of said memory units comprising said system memory and means for regulating the transfer of data associated with given memory commands to and from said SCU and addressed segments of a corresponding memory unit in said system memory.

Claim 2

Dependent Claim 78 words

The multi-processing system of claim 2 wherein said memory commands accepted and decoded by said interface means include an index associated therewith, and said interface means includes means for ascertaining whether or not a memory command addresses an available segment of memory, and means for relaying said index back to said SCU if the segment being addressed is available, for thereby initiating transfer of the address associated with said memory command from the SCU to said system memory.

Claim 3

Dependent Claim 58 words

The multi-processing system of claim 3 wherein the interface means further includes means for detecting when a later memory command addresses a memory segment which is currently being accessed by a former memory command and delaying the return of the index associated with the later command to said SCU until said memory segment is available to be accessed.

Claim 4

Dependent Claim 40 words

The multi-processing system of claim 4 wherein said relaying means in said interface means also relays back with said index a signal indicative of the particular row or column being addressed in a memory segment by the associated memory command.

Claim 5

Dependent Claim 86 words

The multi-processing system of claim 2 wherein said means for regulating data transfer in said interface means includes means for accepting data associated with a memory command from said SCU over a first data path disposed between the SCU and said interface means, means for transferring said data to said memory unit linked to said interface means, and means for accepting from said memory unit data corresponding to a memory command from said SCU and transferring said data to said SCU over said first data path.

Claim 6

Dependent Claim 138 words

A multi-processing system of the kind having a system control unit (SCU) for operating a plurality of processors in a parallel fashion in combination with at least one input/output (I/O) unit, wherein the improvement comprises: (a) at least one main memory unit (MMU) containing independently accessible DRAM-based memory segments, and (b) dedicated interface means disposed between the SCU and a MMU, said dedicated interface means including (i) means for accepting memory commands from a CPU or I/O unit through the SCU, said memory commands including executable addresses which address available ones of said memory segments and non-executable addresses which address non-available ones of said memory segments, and (ii) means for executing the memory commands which address said available memory segments by the transfer of data associated with the commands between the SCU and the corresponding addressed memory segments.

Claim 7

Dependent Claim 138 words

A multi-processing system of the kind having a system control unit (SCU) for operating a plurality of processors in a parallel fashion in combination with at least one input/output (I/O) unit, wherein the improvement comprises: (a) at least one main memory unit (MMU) containing independently accessible DRAM-based memory segments, and (b) dedicated interface means disposed between the SCU and a MMU, said dedicated interface means including (i) means for accepting memory commands from a CPU or I/O unit through the SCU, said memory commands including executable addresses which address available ones of said memory segments and non-executable addresses which address non-available ones of said memory segments, and (ii) means for executing the memory commands which address said available memory segments by the transfer of data associated with the commands between the SCU and the corresponding addressed memory segments.

Claim 8

Dependent Claim 56 words

The multi-processing system of claim 7 wherein the interface means is linked to the SCU and a corresponding MMU through control lines for transfer of memory command data, data path lines for transfer of data associated with memory commands, and address path lines for transfer of data designating addressed segments of memory associated with memory commands.

Claim 9

Dependent Claim 84 words

9 The multi-processing system of claim 8 wherein, said interface means comprises: a macrocell array control unit (ACU) including main memory control (MMC) means for providing control signals for the data path, the address path and the DRAMs included in said memory segments; memory data path (MDP) means for regulating the bi-directional transfer of data over said data path; and memory controller DRAM (MCD) means for controlling the operation, including loading and unloading, of DRAMs included in said memory segments of said system memory.

Claim 10

Independent Claim 208 words

A method for operating a multi-processing computer system comprising a plurality of system units including a plurality of central processing units (CPUs) and at least one input/output (I/O) unit, and a system memory for storage of data, said memory comprising at least one memory unit containing independently accessible memory segments, said method comprising the steps of providing a system control unit (SCU) for operating said CPUs in a parallel fashion and allowing said CPUs and other system units to controllably access addressed segments of memory, said SCU operating to accept memory commands from said system units, decode memory addresses accompanying said memory commands, and accommodate transfer of data to and from a system unit originating a memory command and corresponding addressed memory segments; providing dedicated interface means for establishing communication between said SCU and said system memory, said interface means being linked on one end to said SCU and on the other end to a memory unit comprising said system memory; and operating said interface means being allow memory commands received from said SCU to be controllably executed by accessing corresponding addressed segments in a memory unit and transferring data associated with said commands to and from said SCU and said corresponding addressed segments in a memory unit.

Claim 11

Independent Claim 208 words

A method for operating a multi-processing computer system comprising a plurality of system units including a plurality of central processing units (CPUs) and at least one input/output (I/O) unit, and a system memory for storage of data, said memory comprising at least one memory unit containing independently accessible memory segments, said method comprising the steps of providing a system control unit (SCU) for operating said CPUs in a parallel fashion and allowing said CPUs and other system units to controllably access addressed segments of memory, said SCU operating to accept memory commands from said system units, decode memory addresses accompanying said memory commands, and accommodate transfer of data to and from a system unit originating a memory command and corresponding addressed memory segments; providing dedicated interface means for establishing communication between said SCU and said system memory, said interface means being linked on one end to said SCU and on the other end to a memory unit comprising said system memory; and operating said interface means being allow memory commands received from said SCU to be controllably executed by accessing corresponding addressed segments in a memory unit and transferring data associated with said commands to and from said SCU and said corresponding addressed segments in a memory unit.

Claim 12

Dependent Claim 82 words

The method of operating a multi-processing system as set forth in claim 11 wherein said interface means is operated to accept and decode memory commands and associated data from said SCU, to regulate the transfer of decoded commands and corresponding memory addresses to corresponding ones of said memory units comprising said system memory and to regulate the transfer of data associated with given memory commands to and from said SCU and addressed segments of a corresponding memory unit in said system memory.

Claim 13

Dependent Claim 77 words

The method set forth in claim 10 wherein said memory commands accepted and decoded by said interface means include an index associated therewith, and said interface means is operated to ascertain whether or not a memory command addresses an available segment of memory, and to relay said index back to said SCU if the segment being addressed is available, thereby initiating transfer of the address associated with said memory command from the SCU to said system memory.

Claim 14

Dependent Claim 58 words

The method of claim 12 wherein the interface means is further operated to detect when a later memory command addresses a memory segment which is currently being accessed by a former memory command and to delay the return of the index associated with the later command to said SCU until said memory segment is available to be accessed.

Claim 15

Dependent Claim 38 words

The method of claim 13 wherein said interface means is operated to also relay back with said index a signal indicative of the particular row or column being addressed in a memory segment by the associated memory command.

Claim 16

Dependent Claim 77 words

The method of claim 14 wherein said interface means is also operated to accept data associated with a memory command from said SCU over a first data path disposed between the SCU and said interface means to transfer said data to said memory unit linked to said interface means, and to accept from said memory unit data corresponding to a memory command from said SCU and transfer said data to said SCU over said first data path.

Claim 17

Independent Claim 145 words

A method of operating a multi-processing system of the kind having a system control unit (SCU) for operating a plurality of processors in a parallel fashion in combination with at least one input/output (I/O) unit, said method comprising the steps of: (a) using at least one main memory unit (MMU) containing independently accessible DRAM-based memory segments, (b) providing dedicated interface means disposed between the SCU and a MMU, and (c) operating said dedicated interface means to (i) accept memory commands from a CPU or I/O unit through the SCU, said memory commands including executable addresses which address available ones of said memory segments and non-executable addresses which address non-available ones of said memory segments, and (ii) to execute the memory commands which address said available memory segments by the transfer of data associated with the commands between the SCU and the corresponding addressed memory segments.

Claim 18

Independent Claim 145 words

A method of operating a multi-processing system of the kind having a system control unit (SCU) for operating a plurality of processors in a parallel fashion in combination with at least one input/output (I/O) unit, said method comprising the steps of: (a) using at least one main memory unit (MMU) containing independently accessible DRAM-based memory segments, (b) providing dedicated interface means disposed between the SCU and a MMU, and (c) operating said dedicated interface means to (i) accept memory commands from a CPU or I/O unit through the SCU, said memory commands including executable addresses which address available ones of said memory segments and non-executable addresses which address non-available ones of said memory segments, and (ii) to execute the memory commands which address said available memory segments by the transfer of data associated with the commands between the SCU and the corresponding addressed memory segments.

Claim 19

Dependent Claim 63 words

The method of operating a multi-processing system as set forth in claim 16 wherein the interface means is linked to the SCU and a corresponding MMU through control lines for transfer of memory command data, data path lines for transfer of data associated with memory commands, and address path lines for transfer of data designating addressed segments of memory associated with memory commands.

Claim 20

Dependent Claim 62 words

The method of claim 17 wherein, said interface means is further operated to provide control signals for the data path, the address path and the DRAMs included in said memory segments to regulate the bi-directional transfer of data over said data path and to control the operation, including loading and unloading, of DRAMs included in said memory segments of said system memory.

Method and means for interfacing a system control unit for a multi-processor system with the system main memory

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