Write-read/write-pass memory subsystem cycle

Claim 2

For a digital computer system including a system control unit (SCU) with a main memory and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, a method of transferring requested data to a requesting one of the CPU's from the cache of a selected one of said other CPU's through said SCU and concurrently refreshing said SCU main memory, comprising the steps of: transmitting said requested data from said selected CPU to said SCU; checking the validity of said transmitted data to establish confirmed data; transmitting said confirmed data to said requesting CPU; and, writing said confirmed data in said SCU main memory at a selected address.

Claim 3

The method recited in claim 1, wherein said step of checking establishes unconfirmed data when said transmitted data is not entirely valid, and then further comprises the step of: determining the validity of portions of said unconfirmed data to establish validified portions of said unconfirmed data; writing said validified portions in said SCU main memory at a selected address; reading data from said SCU main memory at said selected address; and, transmitting said read data to said requesting CPU.

Claim 4

For a digital computer system including a system control unit (SCU) with a main memory and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, a method of transferring requested data to a requesting one of the CPU's from the cache of a selected one of said other CPU's through said SCU and concurrently refreshing said SCU main memory, comprising the steps of: transmitting said requested data from said selected CPU to said SCU; determining that said transmitted data is not valid to establish unconfirmed data; determining the validity of portions of said unconfirmed data to establish validified portions of said unconfirmed data; writing said validified portions in said SCU main memory at a selected address; reading data from said SCU main memory at said selected address; and, transmitting said read data to said requesting CPU.

Claim 5

For a digital computer system including a system control unit (SCU) with a main memory and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, a method of transferring requested data to a requesting one of the CPU's from the cache of a selected one of said other CPU's through said SCU and concurrently refreshing said SCU main memory, comprising the steps of: transmitting said requested data from said selected CPU to said SCU; determining that said transmitted data is not valid to establish unconfirmed data; determining the validity of portions of said unconfirmed data to establish validified portions of said unconfirmed data; writing said validified portions in said SCU main memory at a selected address; reading data from said SCU main memory at said selected address; and, transmitting said read data to said requesting CPU.

Claim 6

For a digital computer system including a system control unit (SCU) with a main memory and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, a method of transferring requested data to a requesting one of the CPU's from the cache of a selected one of said other CPU's through said SCU and concurrently refreshing said SCU main memory, comprising the steps of: transmitting said requested data from said selected CPU to said SCU; checking the validity of said transmitted data, to establish confirmed data or unconfirmed data; if said transmitted data is established as confirmed data then (a) transmitting said confirmed data to said requesting CPU; and (b) writing said confirmed data in said SCU main memory at a selected address; or, if said transmitted data is established as unconfirmed data then (a) determining the validity of portions of said unconfirmed data to establish validified portions of said unconfirmed data; (b) writing said validified portions in said SCU main memory at a selected address; (c) reading data from said SCU main memory at said selected address; and (d) transmitting said read data to said requesting CPU.

Claim 7

For a digital computer system including a system control unit (SCU) with a main memory and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, a method of transferring requested data to a requesting one of the CPU's from the cache of a selected one of said other CPU's through said SCU and concurrently refreshing said SCU main memory, comprising the steps of: transmitting said requested data from said selected CPU to said SCU; checking the validity of said transmitted data, to establish confirmed data or unconfirmed data; if said transmitted data is established as confirmed data then (a) transmitting said confirmed data to said requesting CPU; and (b) writing said confirmed data in said SCU main memory at a selected address; or, if said transmitted data is established as unconfirmed data then (a) determining the validity of portions of said unconfirmed data to establish validified portions of said unconfirmed data; (b) writing said validified portions in said SCU main memory at a selected address; (c) reading data from said SCU main memory at said selected address; and (d) transmitting said read data to said requesting CPU.

Claim 8

For a digital computer system including a system control unit (SCU) with a main memory and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, a method of transferring requested data to a requesting one of the CPU's from the cache of a selected one of said other CPU's through said SCU and concurrently refreshing said SCU main memory, comprising the steps of: receiving command information from said SCU; decoding a memory address in said main memory for said requested data from said command information; transmitting said decoded address to said main memory; locking said decoded address in said main memory; transferring said requested data from said selected CPU to said SCU; checking the validity of said requested data from said selected CPU; if said requested data from said selected CPU is established as confirmed data then (a) transmitting said confirmed data to said requesting CPU; and (b) writing said confirmed data in said main memory at said decoded address; or, if said transmitted data is established as unconfirmed data then (a) determining the validity of portions of said unconfirmed data to establish validified portions of said unconfirmed data; (b) writing said validified portions in said main memory at said decoded address; (c) reading data from said main memory at said decoded address; and (d) transmitting said read data to said requesting CPU.

Claim 9

For a digital computer system including a system control unit (SCU) with a main memory and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, a method of transferring requested data to a requesting one of the CPU's from the cache of a selected one of said other CPU's through said SCU and concurrently refreshing said SCU main memory, comprising the steps of: receiving command information from said SCU; decoding a memory address in said main memory for said requested data from said command information; transmitting said decoded address to said main memory; locking said decoded address in said main memory; transferring said requested data from said selected CPU to said SCU; checking the validity of said requested data from said selected CPU; if said requested data from said selected CPU is established as confirmed data then (a) transmitting said confirmed data to said requesting CPU; and (b) writing said confirmed data in said main memory at said decoded address; or, if said transmitted data is established as unconfirmed data then (a) determining the validity of portions of said unconfirmed data to establish validified portions of said unconfirmed data; (b) writing said validified portions in said main memory at said decoded address; (c) reading data from said main memory at said decoded address; and (d) transmitting said read data to said requesting CPU.

Claim 10

In a digital computer system including a system control unit (SCU) with a main memory and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, apparatus for transferring requested data to a requesting one of the CPU's from the cache of a selected one of said other CPU's through said SCU and concurrently refreshing said SCU main memory, comprising: means for transmitting said requested data from said selected CPU to said SCU; means for checking the validity of said transmitted data to establish confirmed data; means for transmitting said confirmed data to said requesting CPU; and, means for writing said confirmed data in said SCU main memory at a selected address.

Claim 11

In a digital computer system including a system control unit (SCU) with a main memory and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, apparatus for transferring requested data to a requesting one of the CPU's from the cache of a selected one of said other CPU's through said SCU and concurrently refreshing said SCU main memory, comprising: means for transmitting said requested data from said selected CPU to said SCU; means for checking the validity of said transmitted data to establish confirmed data; means for transmitting said confirmed data to said requesting CPU; and, means for writing said confirmed data in said SCU main memory at a selected address.

Claim 12

The apparatus recited in claim 6, wherein said means for checking establishes unconfirmed data when said transmitted data is not entirely valid and further comprising: means for determining the validity of portions of said unconfirmed data to establish validified portions of said unconfirmed data; means for writing said validified portions in said SCU main memory at said selected address; means for reading data from said SCU main memory at said selected address; and, means for transmitting said read data to said requesting CPU.

Claim 13

In a digital computer system including a system control unit (SCU) with a main memory and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, apparatus for transferring requested data to a requesting one of the CPU's from the cache of a selected one of said other CPU's through said SCU and concurrently refreshing said SCU main memory, comprising: means for transmitting said requested data from said selected CPU to said SCU; means for determining that said transmitted data is not valid to establish unconfirmed data; means for determining the validity of portions of said unconfirmed data to establish validified portions of said unconfirmed data; means for writing said validified portions in said SCU main memory at a selected address; means for reading data from said SCU main memory at said selected address; and, means for transmitting said read data to said requesting CPU.

Claim 14

In a digital computer system including a system control unit (SCU) with a main memory and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, apparatus for transferring requested data to a requesting one of the CPU's from the cache of a selected one of said other CPU's through said SCU and concurrently refreshing said SCU main memory, comprising: means for transmitting said requested data from said selected CPU to said SCU; means for determining that said transmitted data is not valid to establish unconfirmed data; means for determining the validity of portions of said unconfirmed data to establish validified portions of said unconfirmed data; means for writing said validified portions in said SCU main memory at a selected address; means for reading data from said SCU main memory at said selected address; and, means for transmitting said read data to said requesting CPU.

Claim 15

In a digital computer system including a system control unit (SCU) with a main memory and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, apparatus for transferring requested data to a requesting one of the CPU's from the cache of a selected one of said other CPU's through said SCU and concurrently refreshing said SCU main memory, comprising: means for transmitting said requested data from said selected CPU to said SCU; means for checking the validity of said transmitted data, to establish confirmed data or unconfirmed data; means for transmitting said confirmed data to said requesting CPU; means for writing said confirmed data in said SCU main memory at a selected address; means for determining the validity of portions of said unconfirmed data to establish validified portions of said unconfirmed data; means for writing said validified portions in said SCU main memory at said selected address; means for reading data from said SCU main memory at said selected address; and, means for transmitting said read data to said requesting CPU.

Claim 16

In a digital computer system including a system control unit (SCU) with a main memory and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, apparatus for transferring requested data to a requesting one of the CPU's from the cache of a selected one of said other CPU's through said SCU and concurrently refreshing said SCU main memory, comprising: means for transmitting said requested data from said selected CPU to said SCU; means for checking the validity of said transmitted data, to establish confirmed data or unconfirmed data; means for transmitting said confirmed data to said requesting CPU; means for writing said confirmed data in said SCU main memory at a selected address; means for determining the validity of portions of said unconfirmed data to establish validified portions of said unconfirmed data; means for writing said validified portions in said SCU main memory at said selected address; means for reading data from said SCU main memory at said selected address; and, means for transmitting said read data to said requesting CPU.

Claim 17

In a digital computer system including a system control unit (SCU) with a main memory and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, apparatus for transferring requested data to a requesting one of the CPU's from the cache of a selected one of said other CPU's through said SCU and concurrently refreshing said SCU main memory, comprising: means for receiving command information from said SCU; means for decoding a memory address for said requested data from said command information; means for transmitting said decoded address to said main memory; means for locking said decoded address in said main memory; means for transferring said requested data from said selected CPU to said SCU; means for checking the validity of said requested data to establish confirmed data or unconfirmed data; means for transmitting said confirmed data to said requesting CPU; means for writing said confirmed data in said main memory at said decoded address; means for determining the validity of portions of said unconfirmed data to establish validified portions of said unconfirmed data; means for writing said validified portions in said main memory system at said decoded address; means for reading data from said main memory at said decoded address; and means for transmitting said read data to said requesting CPU.

Claim 18

In a digital computer system including a system control unit (SCU) with a main memory and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, apparatus for transferring requested data to a requesting one of the CPU's from the cache of a selected one of said other CPU's through said SCU and concurrently refreshing said SCU main memory, comprising: means for receiving command information from said SCU; means for decoding a memory address for said requested data from said command information; means for transmitting said decoded address to said main memory; means for locking said decoded address in said main memory; means for transferring said requested data from said selected CPU to said SCU; means for checking the validity of said requested data to establish confirmed data or unconfirmed data; means for transmitting said confirmed data to said requesting CPU; means for writing said confirmed data in said main memory at said decoded address; means for determining the validity of portions of said unconfirmed data to establish validified portions of said unconfirmed data; means for writing said validified portions in said main memory system at said decoded address; means for reading data from said main memory at said decoded address; and means for transmitting said read data to said requesting CPU.

Claim 19

For a memory device useful with a system control unit (SCU) and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, a method of reducing memory read latency for data transferred from of said CPU's in response to a request for said data from another of said CPU's, comprising the steps of: receiving command information from said SCU; receiving data requested by a requesting one of said CPU's from the cache of a located one of said CPU's; decoding a memory address for said CPU requested data from said command information; latching said decoded memory address; checking the validity of said received data to establish confirmed data; transmitting said confirmed data to said requesting CPU; and, writing said confirmed data at said latched memory address.

Claim 20

For a memory device useful with a system control unit (SCU) and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, a method of reducing memory read latency for data transferred from of said CPU's in response to a request for said data from another of said CPU's, comprising the steps of: receiving command information from said SCU; receiving data requested by a requesting one of said CPU's from the cache of a located one of said CPU's; decoding a memory address for said CPU requested data from said command information; latching said decoded memory address; checking the validity of said received data to establish confirmed data; transmitting said confirmed data to said requesting CPU; and, writing said confirmed data at said latched memory address.

Claim 21

The method recited in claim 11, wherein said step of checking establishes unconfirmed data when said received data is not valid and then further comprising: determining the validity of portions of said unconfirmed data to establish validated portions of said unconfirmed data; writing said validated portions at said latched memory address; reading data from said main memory at said latched memory address; and, transmitting said read data to said requesting CPU.

Claim 22

For a memory device useful with a system control unit (SCU) and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, a method of reducing memory read latency for data transferred from one of said CPU's in response to a request for said data from another of said CPU's, comprising the steps of: receiving command information from said SCU; receiving data requested by a requesting one of said CPU's from the cache of a located one of said CPU's; latching said decoded memory address; determining that said received data is not valid to establish unconfirmed data; determining the validity of portions of said unconfirmed data to establish validated portions of said unconfirmed data; writing said validated portions of said latched memory address; reading data from said main memory at said latched memory address; and, transmitting said read data to said requesting CPU.

Claim 23

For a memory device useful with a system control unit (SCU) and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, a method of reducing memory read latency for data transferred from one of said CPU's in response to a request for said data from another of said CPU's, comprising the steps of: receiving command information from said SCU; receiving data requested by a requesting one of said CPU's from the cache of a located one of said CPU's; latching said decoded memory address; determining that said received data is not valid to establish unconfirmed data; determining the validity of portions of said unconfirmed data to establish validated portions of said unconfirmed data; writing said validated portions of said latched memory address; reading data from said main memory at said latched memory address; and, transmitting said read data to said requesting CPU.

Claim 24

For a memory device useful with a system control unit (SCU) and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, a method of reducing memory read latency for data transferred from one of said CPU's in response to a request for said data from another of said CPU's, comprising the steps of: receiving command information from said SCU; receiving data requested by a requesting one of said CPU's from the cache of a located one of said CPU's; decoding a memory address for said CPU requested data from said command information; latching said decoded memory address; checking the validity of said transmitted data, to establish confirmed data or unconfirmed data; if said transmitted data is established as confirmed data then (a) transmitting said confirmed data to said requesting CPU; and (b) writing said confirmed data in said SCU main memory at a selected address; or, if said transmitted data is established as unconfirmed data then (a) determining the validity of portions of said unconfirmed data to establish validified portions of said unconfirmed data; (b) writing said validified portions of said SCU main memory at a selected address; (c) reading data from said SCU main memory at said selected address; and (d) transmitting said read data to said requesting CPU.

Claim 25

For a memory device useful with a system control unit (SCU) and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, a method of reducing memory read latency for data transferred from one of said CPU's in response to a request for said data from another of said CPU's, comprising the steps of: receiving command information from said SCU; receiving data requested by a requesting one of said CPU's from the cache of a located one of said CPU's; decoding a memory address for said CPU requested data from said command information; latching said decoded memory address; checking the validity of said transmitted data, to establish confirmed data or unconfirmed data; if said transmitted data is established as confirmed data then (a) transmitting said confirmed data to said requesting CPU; and (b) writing said confirmed data in said SCU main memory at a selected address; or, if said transmitted data is established as unconfirmed data then (a) determining the validity of portions of said unconfirmed data to establish validified portions of said unconfirmed data; (b) writing said validified portions of said SCU main memory at a selected address; (c) reading data from said SCU main memory at said selected address; and (d) transmitting said read data to said requesting CPU.

Claim 26

A memory device for use with a system control unit (SCU) and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, providing reduced memory read latency for data transferred from one of said CPU's in response to a request for said data from another of said CPU's, comprising: means for receiving command information from said SCU; means for receiving data requested by a requesting one of said CPU's from the cache of a located one of said CPU's; means for decoding a memory address for said CPU requested data from said command information; means for latching said decoded memory address; means for checking the validity of said received data to establish confirmed data; means for transmitting said confirmed data to said requesting CPU; and, means for writing said confirmed data at said latched memory address.

Claim 27

A memory device for use with a system control unit (SCU) and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, providing reduced memory read latency for data transferred from one of said CPU's in response to a request for said data from another of said CPU's, comprising: means for receiving command information from said SCU; means for receiving data requested by a requesting one of said CPU's from the cache of a located one of said CPU's; means for decoding a memory address for said CPU requested data from said command information; means for latching said decoded memory address; means for checking the validity of said received data to establish confirmed data; means for transmitting said confirmed data to said requesting CPU; and, means for writing said confirmed data at said latched memory address.

Claim 28

The memory device recited in claim 15, wherein said means for checking establishes unconfirmed data when said received data is not valid and further comprising: means for determining the validity of portions of said unconfirmed data to establish validated portions of said unconfirmed data; means for writing said validated portions at said latched memory address; means for reading data from said main memory at said latched memory address; and, means for transmitting said read data to said requesting CPU.

Claim 29

A memory device for use with a system control unit (SCU) and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, providing reduced memory read latency for data transferred from one of said CPU's in response to a request for said data from another of said CPU's, comprising: means for receiving command information from said SCU; means for receiving data requested by a requesting one of said CPU's from the cache of a located one of said CPU's; means for decoding a memory address for said CPU requested data from said command information; means for latching said decoded memory address; means for determining that said received data is not valid to establish unconfirmed data; means for determining the validity of portions of said unconfirmed data to establish validated portions of said unconfirmed data; means for writing said validated portions at said latched memory address; means for reading data from said main memory at said latched memory address; and, means for transmitting said read data to said requesting CPU.

Claim 30

A memory device for use with a system control unit (SCU) and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, providing reduced memory read latency for data transferred from one of said CPU's in response to a request for said data from another of said CPU's, comprising: means for receiving command information from said SCU; means for receiving data requested by a requesting one of said CPU's from the cache of a located one of said CPU's; means for decoding a memory address for said CPU requested data from said command information; means for latching said decoded memory address; means for determining that said received data is not valid to establish unconfirmed data; means for determining the validity of portions of said unconfirmed data to establish validated portions of said unconfirmed data; means for writing said validated portions at said latched memory address; means for reading data from said main memory at said latched memory address; and, means for transmitting said read data to said requesting CPU.

Claim 31

A memory device for use with a system control unit (SCU) and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, providing reduced memory read latency for data transferred from one of said CPU's in response to a request for said data from another of said CPU's, comprising: means for receiving command information from said SCU; means for receiving data requested by a requesting one of said CPU's from the cache of a located one of said CPU's; means for decoding a memory address for said CPU requested data from said command information; means for latching said decoded memory address; means for checking the validity of said received data to establish confirmed data or unconfirmed data; means for transmitting said confirmed data to said requesting CPU; means for writing said confirmed data at said latched memory address; means for determining the validity of portions of said unconfirmed data to establish validated portions of said unconfirmed data; means for writing said validated portions at said latched memory address; means for reading data from said main memory at said latched memory address; and, means for transmitting said read data to said requesting CPU.

Claim 32

A memory device for use with a system control unit (SCU) and a plurality of central processing units (CPU's), each CPU with its own associated writeback cache, providing reduced memory read latency for data transferred from one of said CPU's in response to a request for said data from another of said CPU's, comprising: means for receiving command information from said SCU; means for receiving data requested by a requesting one of said CPU's from the cache of a located one of said CPU's; means for decoding a memory address for said CPU requested data from said command information; means for latching said decoded memory address; means for checking the validity of said received data to establish confirmed data or unconfirmed data; means for transmitting said confirmed data to said requesting CPU; means for writing said confirmed data at said latched memory address; means for determining the validity of portions of said unconfirmed data to establish validated portions of said unconfirmed data; means for writing said validated portions at said latched memory address; means for reading data from said main memory at said latched memory address; and, means for transmitting said read data to said requesting CPU.