Multiple instruction dispatch mechanism

Claim 2

A data processing system comprising: means for storing a plurality of instructions in sequence (10); means for fetching a plurality of instructions; means for dispatching a plurality of instructions (12) to one or more processors (18,20,22) for execution during a single compu­tation cycle; and control means (14) for delaying the dispatching of an instruction when the instruction has an execution result dependent upon a previous instruction execution setting at least one bit in a condition register (16), said instruction delayed until said condition register has been accordingly set.

Claim 3

A data processing system comprising: means for storing a plurality of instructions in sequence (10); means for fetching a plurality of instructions; means for dispatching a plurality of instructions (12) to one or more processors (18,20,22) for execution during a single compu­tation cycle; and control means (14) for delaying the dispatching of an instruction when execution of the instruction will result in a setting of at least one bit in a condition register (16) before a previous instruction execution has completed accessing the at least one bit in the condition register, said instruction delayed until said condition register access has been completed by said previous instruction.

Claim 4

A data processing system comprising: means for storing a plurality of instructions in sequence (10); means for fetching a plurality of instructions; means for dispatching a plurality of instructions (12) to one or more processors (18,20,22) for execution during a single compu­tation cycle; and control means (14) for delaying the dispatching of an instruction when execution of the instruction will result in a setting of at least one bit in a condition register (16) before a previous instruction execution has completed accessing the at least one bit in the condition register, said instruction delayed until said condition register access has been completed by said previous instruction.

Claim 5

A data processing system as claimed in Claim 1 or Claim 2 wherein said fetching means includes means for fetching said plurality of instructions in a single computation cycle.

Claim 6

A data processing system as claimed in any preceding claim wherein said condition register includes a plurality of fields, each field including bits characterizing the result of a predetermined class of instruction execution.

Claim 7

A data processing system as claimed in any preceding claim wherein each instruction includes a target operand storage designation and at least two source operand storage designations.

Claim 8

A data processing system as claimed in any preceding claim wherein said control means includes means for determining validity of the contents of the condition register.

Claim 9

A data processing system as claimed in any preceding claim wherein said control means includes means for determining if execution of a fetched instruction will modify at least one bit of said condition register.

Claim 10

A data processing system as claimed in any preceding claim wherein said control means includes means for determining if execution of a fetched instruction will read at least one bit of said condition register.

Claim 11

A data processing system comprising: means for storing a plurality of instructions in sequence (10); means for fetching a selection of said plurality of insstructions; a plurality of processors (18,20,22) ; means for dispatching (12) one or more of said fetched instructions to corresponding processors (18,20,22) for execution during a single computation cycle; a condiction register (16) associated with one or more of said processors, said register having one or more bits (Fig 2), control means, connected to said condition register and said associated processor, for setting the state of one or more bits in said condition register, in response to the execution result of the instruction executed in said associated processor during said computation cycle; means for determining whether a current instruction depends on the execution result of a previous instruction in said sequence; means for checking, in the case when the current instruction depends on the execution result of the previous instruction,before execution of said current instruction, by reference to one or more condition register bits associated with said previous instruction, whether said previous instruction has been executed; and means, responsive to said means for checking, for delaying the execution of said current instructin until said previous instruction has been executed, in the case when the current instruction depends on the execution result of the previous instruction.

Claim 12

A data processing system comprising: means for storing a plurality of instructions in sequence (10); means for fetching a selection of said plurality of insstructions; a plurality of processors (18,20,22) ; means for dispatching (12) one or more of said fetched instructions to corresponding processors (18,20,22) for execution during a single computation cycle; a condiction register (16) associated with one or more of said processors, said register having one or more bits (Fig 2), control means, connected to said condition register and said associated processor, for setting the state of one or more bits in said condition register, in response to the execution result of the instruction executed in said associated processor during said computation cycle; means for determining whether a current instruction depends on the execution result of a previous instruction in said sequence; means for checking, in the case when the current instruction depends on the execution result of the previous instruction,before execution of said current instruction, by reference to one or more condition register bits associated with said previous instruction, whether said previous instruction has been executed; and means, responsive to said means for checking, for delaying the execution of said current instructin until said previous instruction has been executed, in the case when the current instruction depends on the execution result of the previous instruction.