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EP0378301A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Transmitter/receiver apparatus

Assignee: Citizen Watch Co Ltd
•
Filing: 1990-01-04
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Granted: —
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Expires: 2010-01-04
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Abstract

Abstract A transmitter/receiver apparatus includes a trans­mitter and a receiver. The transmitter includes an inter­mittent signal generator and an intermittent modulator. The intermittent signal generator generates an intermittent signal. The intermittent modulator outputs an intermittent modulated signal, as a radio signal, which is obtained by intermittently modulating a carrier on the basis of the intermittent signal. The receiver includes a synchro­nization determining circuit and a synchronization detector. The synchronization determining circuit has a receiving circuit for receiving the radio signal from the transmitter and outputting a demodulated signal and is de­signed to detect the presence/absence of the demodulated signal and output a determining signal. The synchro­nization detector generates an intermittent sync signal having the same period as that of the intermittent signal from the transmitter, and performs a synchronization de­tecting operation with respect to the intermittent signal from the transmitter on the basis of the intermittent sync signal and the determining signal from the synchronization determining circuit. The intermittent signal generator of the transmitter generates intermittent signals having in­tervals which cyclically change.

Inventors

  • 👤 Tadishi Yasuoka

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-02 23:14
CPC Classifications
G; G08; G08B; G08B21/00; G08B21/02; G08B21/0202; G08B21/0222; G08B13/00; G08B13/02; G08B13/14; G08B13/1427; G08B21/023

Claims Analysis

Total Claims: 14
Claim 1
Independent Claim 152 words
A transmitter/receiver apparatus comprising: (a) a transmitter including an intermittent signal generator for generating an intermittent signal, and an intermittent modulator for outputting an intermittently modulated signal, as a radio signal, which is obtained by intermittently modulating a carrier on the basis of the intermittent signal ; and (b) a receiver including a synchronization determining circuit, having a receiving circuit for receiving the radio signal from said transmitter and outputting a demodulated signal, for detecting the demodulated signal and outputting a determining signal, and a synchronization detector for generating an intermittent sync. signal having the same period as that of the intermittent signal from said trans­mitter, and detecting synchronization operation with respect to the intermittent signal from said transmitter on the basis of the intermittent sync. signal and the determining signal from said synchronization determining circuit, wherein said intermittent signal generator of said trans­mitter generates intermittent signals having intervals which cyclically change.
Claim 2
Dependent Claim 152 words
A transmitter/receiver apparatus comprising: (a) a transmitter including an intermittent signal generator for generating an intermittent signal, and an intermittent modulator for outputting an intermittently modulated signal, as a radio signal, which is obtained by intermittently modulating a carrier on the basis of the intermittent signal ; and (b) a receiver including a synchronization determining circuit, having a receiving circuit for receiving the radio signal from said transmitter and outputting a demodulated signal, for detecting the demodulated signal and outputting a determining signal, and a synchronization detector for generating an intermittent sync. signal having the same period as that of the intermittent signal from said trans­mitter, and detecting synchronization operation with respect to the intermittent signal from said transmitter on the basis of the intermittent sync. signal and the determining signal from said synchronization determining circuit, wherein said intermittent signal generator of said trans­mitter generates intermittent signals having intervals which cyclically change.
Claim 3
Dependent Claim 80 words
An apparatus according to claim 1, wherein said intermittent signal generator comprises an oscillator, a frequency divider for frequency-dividing an oscillation output from said oscillator at predetermined frequency division ratios, a selection gate for selecting a plurality of pulse signals having different periods by using frequency-­divided signals from said frequency divider, and an inter­mittent signal forming circuit for receiving the plurality of pulse signals from said selection gate and outputting intermittent signals whose intervals cyclically change in a predetermined order.
Claim 4
Dependent Claim 61 words
An apparatus according to claim 2, wherein said frequency divider comprises a sync. frequency divider which is instantaneously reset by an intermittent signal, and said selection gate is designed to selectively output a plurality of pulse signals having different periods on the basis of frequency-divided signals which are output at a timing when or after said sync. frequency divider is reset.
Claim 5
Dependent Claim 106 words
An apparatus according to claim 2, wherein said intermittent signal forming circuit comprises a synchro­nization storage circuit having a plurality of intermittent signal designating terminals for outputting designating signals corresponding to the plurality of pulse signals having different periods output from said selection gate, and a plurality of gates for receiving the plurality of pulse signals having different periods output from said selection gate and the designating signals output from said plurality of intermittent signal designating terminals of said synchronization storage circuit, said plurality of gates outputting only pulses of a plurality of input pulse signals, that are designated by the designating signals as intermittent signals.
Claim 6
Dependent Claim 53 words
An apparatus according to claim 4, wherein said synchronization storage circuit comprises a clock terminal for receiving an intermittent signal, and a cyclic des­ignating circuit for cyclically switching an output order of designating signals output from said intermittent signal designating terminals on the basis of the intermittent sig­nal input to said clock terminal.
Claim 7
Dependent Claim 80 words
An apparatus according to claim 1, wherein said synchronization detector comprises an oscillator, a fre­quency divider for frequency-dividing an oscillation output from said oscillator at predetermined frequency division ratios, a selection gate for selecting a plurality of pulse signals having different periods by using frequency-divided signals from said frequency divider, and a sync signal forming circuit for receiving the plurality of pulse signals from said selection gate and outputting intermit­tent sync signals whose intervals cyclically change in a predetermined order.
Claim 8
Dependent Claim 34 words
An apparatus according to claim 6, wherein said synchronization detector further comprises a pulse width increasing circuit for increasing a pulse width of an intermittent sync. signal output from said sync. signal form­ing circuit.
Claim 9
Dependent Claim 61 words
An apparatus according to claim 6, wherein said frequency divider comprises a sync. frequency divier which is instantaneously reset by a determining signal, and said selection gate is designed to selectively output a plurality of pulse signals having different periods on the basis of frequency-divided signals which are output at a timing when or after said sync. frequency divider is reset.
Claim 10
Dependent Claim 107 words
An apparatus according to claim 6, wherein said sync signal forming circuit comprises a synchronization storage circuit having a plurality of intermittent signal designating terminals for outputting designating signals corresponding to the plurality of pulse signals having different periods output from said selection gate, and a plurality of gates for receiving the plurality of pulse signals having different periods output from said selection gate and the designating signals output from said plurality of intermittent signal designating terminals of said syn­chronization storage circuit, said plurality of gates out­putting only pulses of a plurality of input pulse signals that are designated by the designating signals as inter­mittent sync. signals.
Claim 11
Dependent Claim 54 words
An apparatus according to claim 9, wherein said synchronization storage circuit comprises a clock terminal for receiving an intermittent signal, and a cyclic designating circuit for cyclically switching an output order of designating signals output from said intermittent signal designating terminals on the basis of the inter­mittent sync. signal input to said clock terminal.
Claim 12
Independent Claim 225 words
A method of detecting initial synchronization of a transmitter/receiver comprises the steps of: (a) generating an initializing pulse; (b) resetting a mode switching circuit by the initializing pulse, and outputting a continuous mode signal; (c) detecting a radio signal which is output from a transmitter in response to the continuous mode signal, continuously operating a synchronization determining circuit for outputting a determining signal, and holding a synchro­nization detector in a reset state; (d) canceling the reset state of said mode switch­ing circuit and stopping output of the continuous mode signal by a first determining signal from said synchroni­zation determining circuit; (e) setting said synchronization determining cir­cuit in an inoperative state and canceling the reset state of said synchronization detector upon stop of the continu­ous mode signal; (f) starting a cyclic designating operation upon cancellation of the reset state so as to cause said syn­chronization detector to output a plurality of intermittent sync signals included in one cycle in a predetermined or­der; (g) operating said synchronization determining circuit in response to the intermittent sync signal; (h) causing said synchronization detector to store an order of synchronization by detecting a second determin­ing signal and an intermittent sync signal synchronized therewith; and (i) causing said synchronization detector and said synchronization determining circuit to start an intermit­tent synchronization mode in the order of synchronization stored in said synchronization detector.
Claim 13
Independent Claim 225 words
A method of detecting initial synchronization of a transmitter/receiver comprises the steps of: (a) generating an initializing pulse; (b) resetting a mode switching circuit by the initializing pulse, and outputting a continuous mode signal; (c) detecting a radio signal which is output from a transmitter in response to the continuous mode signal, continuously operating a synchronization determining circuit for outputting a determining signal, and holding a synchro­nization detector in a reset state; (d) canceling the reset state of said mode switch­ing circuit and stopping output of the continuous mode signal by a first determining signal from said synchroni­zation determining circuit; (e) setting said synchronization determining cir­cuit in an inoperative state and canceling the reset state of said synchronization detector upon stop of the continu­ous mode signal; (f) starting a cyclic designating operation upon cancellation of the reset state so as to cause said syn­chronization detector to output a plurality of intermittent sync signals included in one cycle in a predetermined or­der; (g) operating said synchronization determining circuit in response to the intermittent sync signal; (h) causing said synchronization detector to store an order of synchronization by detecting a second determin­ing signal and an intermittent sync signal synchronized therewith; and (i) causing said synchronization detector and said synchronization determining circuit to start an intermit­tent synchronization mode in the order of synchronization stored in said synchronization detector.
Claim 14
Dependent Claim 27 words
A method according to claim 11, wherein the step (f) comprises causing said synchronization detector to sequentially output intermittent sync signals in the order of shorter intervals.

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