EP0377990A2
Expired / Lapsed
EP
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Data processing systems
Assignee: International Business Machines Corp
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Filing: 1989-12-20
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Granted: —
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Expires: 2009-12-20
Abstract
Abstract A data processing system including a first processor that performs fixed point arithmetic operations and a second processor that performs floating point arithmetic operations. These two processors are connected by control circuitry that decodes a floating point arithmetic instruction that requires the second processor to perform a specified floating point arithmetic operation. The control circuitry provides information to the first processor to enable the first processor to compute a memory address for accessing the floating point data required by the second processor for performing the specified floating point arithmetic operation. Simultaneously the control circuitry provides the second processor with the information to initiate the execution of the specified floating point arithmetic operation. Also, the data processing system includes the means to access multi-word floating point data on either even or odd memory address boundaries.
Inventors
- 👤 Myhong Nguyenphu
- 👤 Larry Edward Thatcher
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 03:13
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3816; G06F9/34; G06F9/3818; G06F9/3822; G06F9/3824; G06F9/3877; G06F9/3885
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
94 words
A data processing system comprising: a first processor means for performing fixed point arithmetic operations; a second processor means for performing floating point arithmetic operations; control means connected to the first and second processor means for decoding a floating point arithmetic instruction requiring the second processor means to perform a specified floating point arithmetic operation and providing information to the first processor means for computing a memory address for floating point data for the second processor means while providing information to the second processor means for execution of the specified floating point arithmetic operation.
Claim 2
Dependent Claim
94 words
A data processing system comprising: a first processor means for performing fixed point arithmetic operations; a second processor means for performing floating point arithmetic operations; control means connected to the first and second processor means for decoding a floating point arithmetic instruction requiring the second processor means to perform a specified floating point arithmetic operation and providing information to the first processor means for computing a memory address for floating point data for the second processor means while providing information to the second processor means for execution of the specified floating point arithmetic operation.
Claim 3
Dependent Claim
40 words
A system as claimed in Claim 1, wherein the first processor means includes means for fetching from a memory the floating point data at the memory address computed by the first processor means and for providing the floating point data.
Claim 4
Dependent Claim
18 words
A system as claimed in Claim 2, wherein the floating point data includes a plurality of data words.
Claim 5
Dependent Claim
48 words
A system as claimed in Claim 3, wherein the control means further includes means for loading the plurality of data words of the floating point data and wherein a first of the data words was stored in either an even or an odd address location of the memory.
Claim 6
Dependent Claim
51 words
A system as claimed in Claim 4, wherein the second processor means is connect to receive the floating point data on a data bus which includes an even data bus line for transferring data form even memory addresses and an odd data bus line for transferring data from odd memory address.
Claim 7
Dependent Claim
77 words
A system as claimed in Claim 5, wherein the second processor means includes loading means connected to the even data bus line, the odd data bus line and the control means for providing the first of the plurality of floating point data words to a first floating point register in the second processor means and a second of the plurality of the floating point data words to a second floating point register of the second processor means.
Claim 8
Dependent Claim
45 words
A system as claimed in Claim 6, wherein the second processor means includes a first multiplexor for loading a data word from either the odd data bus line or the even data bus line into the first floating point register of the second processor means.
Claim 9
Dependent Claim
45 words
A system as claimed in Claim 7, wherein the second processor means includes a second multiplexor for loading a data word from either the odd data bus line or the even data bus line into the second floating point register of the second processor means.
Claim 10
Dependent Claim
45 words
A system as claimed in Claim 8, wherein the second processor means first multiplexor includes means for loading data from the first floating point register on to either the even data bus line or the odd data bus line as specified by the control means.
Claim 11
Dependent Claim
45 words
A system as claimed in Claim 9, wherein the second processor means second multiplexor includes means for loading data from the second floating point register on to either the even data bus line or the odd data bus line as specified by the control means.
References Cited (Backward Citations)
No citation records indexed.
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