EP0377840A2
Expired / Lapsed
EP
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Nonvolatile semiconductor memory device having reference potential generating circuit
Assignee: Toshiba Corp
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Filing: 1989-12-12
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Granted: —
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Expires: 2009-12-12
Abstract
Abstract A semiconductor memory device includes a memory cell transistor (MCl), a voltage switching circuit (102) supplied with a first voltage for data readout and a second voltage for data write and selectively generating one of the first and second voltages in response to a write control signal, a first driving circuit (112) supplied with an output from the voltage switching circuit (102) and driving the gate of the memory cell transistor (MCl) in response to a memory cell selection signal, a sense circuit (116) for sensing data of the memory cell transistor (MCl) by comparing a sense potential corresponding to data from the memory cell transistor (MCl) with a reference potential, a reference cell transistor (DC) for generating the reference sense potential, and a second driving circuit (12) supplied with the output from the voltage switching circuit (102) and driving the gate of the reference cell transistor (DC) in response to the write control signal.
Inventors
- 👤 Yumiko C/O Intellectual Property Division Iyama
- 👤 Junichi C/O Intellectual Property Div. Miyamoto
- 👤 Nobuaki C/O Intellectual Property Div. Ohtsuka
- 👤 Sumio C/O Intellectual Property Division Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 00:50
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/18; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/28
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
256 words
a semiconductor memory device characterized by comprising: a memory cell (MCl) connected to a ground potential, for storing data, the data being read out from said memory cell (MCl) in a read mode and the data being written into said memory cell (MCl) in a write mode; potential switching means (102) for selectively generating one of first and second potentials in accordance with a mode set as one of the read and write modes, the write mode being set in response to a write control signal and said potential switching means (102) generating the first potential in the read mode and the second potential in the write mode; first driving means (112) for driving said memory cell (MCl) in accordance with one of the first and second potentials from said potential switching means (102) in accordance with a memory cell selection signal which is determined by an input address; sense amplifier means (116) for comparing a sense potential corresponding to the data from said memory cell (MCl) with a reference potential input thereto in the read mode to sense the data stored in said memory cell (MCl); a reference cell (DC) connected to the ground potential, for generating and outputting the reference potential to said sense amplifier means (116) in the read mode; and second driving means (12) connected to the ground potential, for driving said reference cell (DC) in accordance with the reference potential in the write mode and the output of said potential switching means (102) in the read mode as a drive potential.
Claim 2
Dependent Claim
256 words
a semiconductor memory device characterized by comprising: a memory cell (MCl) connected to a ground potential, for storing data, the data being read out from said memory cell (MCl) in a read mode and the data being written into said memory cell (MCl) in a write mode; potential switching means (102) for selectively generating one of first and second potentials in accordance with a mode set as one of the read and write modes, the write mode being set in response to a write control signal and said potential switching means (102) generating the first potential in the read mode and the second potential in the write mode; first driving means (112) for driving said memory cell (MCl) in accordance with one of the first and second potentials from said potential switching means (102) in accordance with a memory cell selection signal which is determined by an input address; sense amplifier means (116) for comparing a sense potential corresponding to the data from said memory cell (MCl) with a reference potential input thereto in the read mode to sense the data stored in said memory cell (MCl); a reference cell (DC) connected to the ground potential, for generating and outputting the reference potential to said sense amplifier means (116) in the read mode; and second driving means (12) connected to the ground potential, for driving said reference cell (DC) in accordance with the reference potential in the write mode and the output of said potential switching means (102) in the read mode as a drive potential.
Claim 3
Dependent Claim
113 words
A device according to claim 1, characterized in that said second driving means (12) comprises: a first transistor (43) connected to a first node, for setting said first node to the ground potential in the read mode; a second transistor (45) connected between said first node and said potential switching means (102), for setting said first node to a potential determined in accordance with the second potential from said potential switching means (102) in the write mode; and a CMOS gate circuit (46) for receiving one of the first and second potentials from said potential switching means (102), for driving said reference cell (DC) in accordance with the potential of said first node.
Claim 4
Dependent Claim
75 words
A device according to claim 2, characterized in that said first transistor (43) is an N-channel transistor having a source connected to receive the write control signal, a gate supplied with the first potential and a drain connected to said first node, and said second transistor (45) is a depletion type N-channel MOS transistor having a drain connected to said potential switching means (102) and a gate and a source connected to said first node.
Claim 5
Dependent Claim
166 words
A device according to claim 1, characterized in that said second driving means (12) comprises: a first transistor (43) connected between first and second nodes, for setting said first node to the ground potential in the read mode, the potential of said second node being set to the ground potential in the read mode and to the first potential in the write mode; a second transistor (45) connected between said first node and said potential switching means (102), for setting said first node to a potential determined in accordance with the second potential from said potential switching means (102) in the write mode; a P-channel MOS transistor (47) supplied with one of the first and second potentials from said potential switching means (102), for driving said reference cell (DC) in accordance with the potential of said first node, and an N-channel MOS transistor (48) connected to said P-channel MOS transistor (47), for driving said reference cell (DC) in accordance with the potential of said second node.
Claim 6
Dependent Claim
84 words
A device according to claim 4, characterized in that said first transistor (43) is an N-channel transistor having a source connected to said second node, a gate supplied with the first potential and a drain connected to said first node; and said second transistor (50) is a P-channel MOS transistor having a source connected to said voltage switching means (102), a drain connected to said first node and a gate connected to a connection node between said P-channel and N-channel MOS transistors (47, 48).
Claim 7
Dependent Claim
90 words
A device according to claim 1, characterized in that said second driving means (12) comprises: a first transistor (43) for potential separation connected between a terminal to which the write control signal is supplied and a first node; a second transistor (45) connected between said first node and said potential switching means (102) for charging said first node; and a CMOS gate circuit (46) supplied with one of the first and second potentials from said potential switching means (102) for operating in accordance with a potential of said first node.
Claim 8
Dependent Claim
105 words
A device according to claim 1, characterized in that said second driving means (12) comprises: a first transistor (43) for potential separation connected between a terminal to which the write control signal is supplied and a first node; a CMOS gate circuit (47, 48) supplied with one of the first and second potentials from said potentials switching means (102) and connected to receive the write control signal and a signal of said first node; and a second transistor (50) for charging connected between said first node and said potential switching means (102) and having a gate connected to an output of said CMOS gate circuit.
Claim 9
Independent Claim
138 words
A method for protecting a reference cell from an undesired potential stress in the write operation of a semiconductor memory device is characterized by comprising the steps of: applying a first potential to the gate of a memory cell in a read mode to generate a sense potential corresponding to data and applying a second potential for data write to the gate of said memory cell in the write mode; applying a ground potential to a gate of a reference cell in the write mode and applying the first potential to the gate of said reference cell in the read mode so as to generate a reference potential; and comparing the sense potential from said memory cell with the reference potential from said reference cell in the read mode to sense the data stored in said memory cell.
Claim 10
Independent Claim
138 words
A method for protecting a reference cell from an undesired potential stress in the write operation of a semiconductor memory device is characterized by comprising the steps of: applying a first potential to the gate of a memory cell in a read mode to generate a sense potential corresponding to data and applying a second potential for data write to the gate of said memory cell in the write mode; applying a ground potential to a gate of a reference cell in the write mode and applying the first potential to the gate of said reference cell in the read mode so as to generate a reference potential; and comparing the sense potential from said memory cell with the reference potential from said reference cell in the read mode to sense the data stored in said memory cell.
Claim 11
Dependent Claim
96 words
A method according to claim 8, characterized in that the step of applying one of the ground and first potential to the gate of said reference cell comprises the steps of: setting a first node to the ground potential in the read mode; setting said first node to the second potential in the write mode; and applying the ground potential to the gate of said reference cell in the write mode or applying the first potential to the gate of said reference cell in the read mode in accordance with a potential of said first node.
Claim 12
Dependent Claim
121 words
A method according to claim 8, characterized in that the step of applying the potential to the gate of said reference cell comprises the steps of: setting a first node to the ground potential in the read mode; setting a potential of a second node to the ground potential in the read mode and to the first potential in the write mode; setting a potential of said first node to the second potential in the write mode; applying the first potential to the gate of said reference cell in accordance with the potential of said first node in the read mode; and applying the ground potential to the gate of said reference cell according to the potential of said second node.
References Cited (Backward Citations)
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