EP0376568A2 — Read-only memory cell and method of forming same

Claim 1

Independent Claim 109 words

A read-only memory cell, comprising: a transistor having a current path and a control electrode for controlling the conductance of said current path; a word line coupled to said control electrode; a bit line, a first end of said current path coupled to said bit line; a first voltage source representative of a first bit value; a second voltage source representative of a second bit value; and a second end of said current path coupled to a preselected one of said first and second voltage sources, such that a selected one of said bit values may be read from said bit line when said current path is rendered conductive.

Claim 2

Dependent Claim 109 words

A read-only memory cell, comprising: a transistor having a current path and a control electrode for controlling the conductance of said current path; a word line coupled to said control electrode; a bit line, a first end of said current path coupled to said bit line; a first voltage source representative of a first bit value; a second voltage source representative of a second bit value; and a second end of said current path coupled to a preselected one of said first and second voltage sources, such that a selected one of said bit values may be read from said bit line when said current path is rendered conductive.

Claim 3

Dependent Claim 25 words

The memory cell of Claim 1, wherein said first voltage source comprises a drain voltage source, said second voltage source comprising a source voltage source.

Claim 4

Dependent Claim 37 words

The memory cell of Claim 1, wherein transistor comprises a field effect transistor, said current path comprising a channel region, said control electrode comprising a gate insulatively disposed adjacent said channel region for controlling the conductance thereof.

Claim 5

Dependent Claim 136 words

A read-only memory cell formed at a face of a semiconductor layer having a first conductivity type, comprising: a bit line region formed in said semiconductor layer to be of a second conductivity type and having opposed lateral margins, said bit line region coupled to a bit line; a channel region defined in said semiconductor layer adjacent a preselected programmed one of said lateral margins; a voltage source region formed in said semiconductor layer to be of said second conductivity type, said channel region spacing said bit line region from said voltage source region, a voltage source representative of a preselected, programmed one of two bit values coupled to said voltage source region; and a word line conductor insulatively disposed over said channel region such that a predetermined voltage thereon will render said channel region conductive.

Claim 6

Dependent Claim 136 words

A read-only memory cell formed at a face of a semiconductor layer having a first conductivity type, comprising: a bit line region formed in said semiconductor layer to be of a second conductivity type and having opposed lateral margins, said bit line region coupled to a bit line; a channel region defined in said semiconductor layer adjacent a preselected programmed one of said lateral margins; a voltage source region formed in said semiconductor layer to be of said second conductivity type, said channel region spacing said bit line region from said voltage source region, a voltage source representative of a preselected, programmed one of two bit values coupled to said voltage source region; and a word line conductor insulatively disposed over said channel region such that a predetermined voltage thereon will render said channel region conductive.

Claim 7

Dependent Claim 29 words

The memory cell of Claim 4, wherein said voltage source region is coupled to said voltage source by a diffusion region of said second conductivity type formed continuously therewith.

Claim 8

Dependent Claim 115 words

A read-only memory array, comprising: a plurality of transistors formed in rows and columns at an angle to said rows, each transistor having a current path and a control electrode; for each row, a word line coupled to said control electrodes of the transistors in said row; a bit line for each column, first ends of said current paths of respective transistors in said column coupled to said bit line; a first voltage source representative of a first bit value, and a second voltage source representative of a second bit value; and each current path having a second end, each second end coupled to a preselected, programmed one of said first and second voltage sources.

Claim 9

Dependent Claim 115 words

A read-only memory array, comprising: a plurality of transistors formed in rows and columns at an angle to said rows, each transistor having a current path and a control electrode; for each row, a word line coupled to said control electrodes of the transistors in said row; a bit line for each column, first ends of said current paths of respective transistors in said column coupled to said bit line; a first voltage source representative of a first bit value, and a second voltage source representative of a second bit value; and each current path having a second end, each second end coupled to a preselected, programmed one of said first and second voltage sources.

Claim 10

Dependent Claim 23 words

The memory array of Claim 14, wherein said first voltage source comprises a drain voltage, said second voltage source comprising a source voltage.

Claim 11

Dependent Claim 175 words

The memory array of Claim 14, wherein each of said transistors comprises a field effect transistor formed at a face of a semiconductor layer of a first conductivity type, each transistor comprising a bit line region formed at said face to be of a second conductivity type, a first voltage source region of said second conductivity type formed at said face and coupled to said first voltage source, a second voltage source region formed to be of said second conductivity type at said face and coupled to said second voltage source; a first potential channel region disposed in said semiconductor layer between said bit line region and said first voltage source region, a second potential channel region disposed in said semiconductor layer between said bit line region and said second voltage source region; and said bit line coupled to said bit line region, said control electrode comprising a word line conductor insulatively disposed over a preselected, programmed one of said potential channel regions, said preselected one of said potential channel regions forming said current path.

Claim 12

Dependent Claim 124 words

The memory array of Claim 16, wherein each of said plurality of transistors is disposed in a respective cell, said cells formed in said rows and columns; a plurality of elongate word line conductor pairs insulatively disposed over said cells in a row direction such that each cell is intersected by one word line conductor pair, a respective word line conductor insulatively disposed over each said potential channel region; one of said potential channel regions being deselected by disposing a thick insulator layer between said deselected potential channel region and a respective word line conductor, said preselected one of said potential channel regions being selected by disposing a thin gate insulator layer between said preselected potential channel region and said respective word line conductor.

Claim 13

Dependent Claim 49 words

The memory cell of Claim 17, wherein said first voltage source region, said bit line region and said second voltage source region are partially self-aligned by respective lateral margins of said thick insulator layer and the word line conductor associated with said preselected one of said potential channel regions.

Claim 14

Dependent Claim 42 words

The memory array of Claim 16, and further including a diffused region of said second conductivity type elongate in a row direction and continuous with said first voltage source region for coupling said first voltage source region to said first voltage source.

Claim 15

Dependent Claim 42 words

The memory array of Claim 16, and further comprising a diffused region of said second conductivity type elongate in a row direction and continuous with said second voltage source region for coupling said second voltage source region to said second voltage source.

Claim 16

Dependent Claim 142 words

A read-only memory cell, comprising: a first transistor having a current path with first and second ends and a control electrode for controlling the conductance of said current path, said first end of said current path coupled to a source of a voltage representative of a first bit value; a second transistor having a current path with first and second ends and a control electrode for controlling the conductance of the last said current path, said first end of the last said current path coupled to a source of a voltage representative of a second bit value; a word line coupled to said control electrodes; and a bit line coupled to a preselected, programmed one of said second ends such that a programmed one of said bit values may be read on said bit line when said current paths are rendered conductive.

Claim 17

Dependent Claim 142 words

A read-only memory cell, comprising: a first transistor having a current path with first and second ends and a control electrode for controlling the conductance of said current path, said first end of said current path coupled to a source of a voltage representative of a first bit value; a second transistor having a current path with first and second ends and a control electrode for controlling the conductance of the last said current path, said first end of the last said current path coupled to a source of a voltage representative of a second bit value; a word line coupled to said control electrodes; and a bit line coupled to a preselected, programmed one of said second ends such that a programmed one of said bit values may be read on said bit line when said current paths are rendered conductive.

Claim 18

Dependent Claim 235 words

A read-only memory cell formed at a face of a semiconductor layer having a first conductivity type, comprising: spaced-apart first and second regions formed in said semiconductor layer to be of said second conductivity type; a first voltage source region formed in said semiconductor layer to be of said second conductivity type and coupled to a source of a voltage representative of a first bit value, a first channel region defined at said face and of said first conductivity type spacing said first region from said first voltage source region, a first word line gate conductor insulatively disposed adjacent to said first channel region for selectively rendering said first channel region conductive; a second voltage source region formed in said semiconductor layer to be of said second conductivity type and coupled to a source of a voltage representative of a second bit value, a second channel region defined at said face and of said first conductivity type spacing said second region from said second voltage region, a second word line conductor insulatively disposed adjacent to said second channel region for selectively rendering said second channel region conductive, said first and second voltage source regions spaced from each other; and a bit line conductor coupled to a preselected, programmed one of said first and second regions such that a transistor is formed between said bit line conductor and a respective one of said voltage source regions.

Claim 19

Dependent Claim 235 words

A read-only memory cell formed at a face of a semiconductor layer having a first conductivity type, comprising: spaced-apart first and second regions formed in said semiconductor layer to be of said second conductivity type; a first voltage source region formed in said semiconductor layer to be of said second conductivity type and coupled to a source of a voltage representative of a first bit value, a first channel region defined at said face and of said first conductivity type spacing said first region from said first voltage source region, a first word line gate conductor insulatively disposed adjacent to said first channel region for selectively rendering said first channel region conductive; a second voltage source region formed in said semiconductor layer to be of said second conductivity type and coupled to a source of a voltage representative of a second bit value, a second channel region defined at said face and of said first conductivity type spacing said second region from said second voltage region, a second word line conductor insulatively disposed adjacent to said second channel region for selectively rendering said second channel region conductive, said first and second voltage source regions spaced from each other; and a bit line conductor coupled to a preselected, programmed one of said first and second regions such that a transistor is formed between said bit line conductor and a respective one of said voltage source regions.

Claim 20

Dependent Claim 77 words

The memory cell of Claim 22, and further comprising a thick insulator layer disposed outwardly adjacent said gate conductors, said voltage source regions and said first and second regions, said cell programmed by forming a contact orifice through said thick insulator layer to a preselected, programmed one of said first and second regions, said bit line conductor formed so as to substantially fill said contact orifice and contact said preselected one of said first and second regions.

Claim 21

Dependent Claim 140 words

The memory cell of Claim 22, and further comprising a first thick insulator layer disposed outwardly adjacent said gate conductors, said voltage source regions and said first and second regions; contact orifices formed in said first thick insulator layer to expose respective portions of said first and second regions; spaced-apart conductive straps formed over said first thick insulator layer and to fill respective ones of said orifices so as to contact respective ones of said first and second regions; a second thick insulator layer formed over said first thick insulator layer and said conductive straps; and a via orifice formed in said second thick insulator layer to a preselected, programmed one of said conductive straps, a word line conductor formed over said second thick insulator layer and in said via orifice to contact said selected one of said conductive straps.

Claim 22

Independent Claim 199 words

A method for programming a read-only memory cell formed at a face of a semiconductor layer of a first conductivity type, comprising the steps of: defining a cell at the face including a bit line region; forming a thick insulator layer to be disposed outwardly from, and defining, a non-selected channel region of the cell, a first voltage source region of the cell spaced from the bit line region of the cell by the non-selected channel region; forming a gate conductor to be insulatively disposed outwardly from, and defining, a selected channel region of the cell, a second voltage source region of the cell spaced from the bit line region by the selected channel region; using the gate conductor and the thick insulator as masks, implanting exposed regions of the cell with a dopant of a second conductivity type, such that a transistor is formed between the second voltage source region and the bit line region but no transistor is formed between the first voltage source region and the bit line region; coupling the second voltage source region to a source of voltage representative of a predetermined bit value; and coupling the bit line region to a bit line.

Claim 23

Independent Claim 199 words

A method for programming a read-only memory cell formed at a face of a semiconductor layer of a first conductivity type, comprising the steps of: defining a cell at the face including a bit line region; forming a thick insulator layer to be disposed outwardly from, and defining, a non-selected channel region of the cell, a first voltage source region of the cell spaced from the bit line region of the cell by the non-selected channel region; forming a gate conductor to be insulatively disposed outwardly from, and defining, a selected channel region of the cell, a second voltage source region of the cell spaced from the bit line region by the selected channel region; using the gate conductor and the thick insulator as masks, implanting exposed regions of the cell with a dopant of a second conductivity type, such that a transistor is formed between the second voltage source region and the bit line region but no transistor is formed between the first voltage source region and the bit line region; coupling the second voltage source region to a source of voltage representative of a predetermined bit value; and coupling the bit line region to a bit line.

Claim 24

Dependent Claim 46 words

The method of Claim 25, and further comprising the step of forming a diffused region in the semiconductor layer to be of the second conductivity type and continuous with the second voltage source region to couple the second voltage source region to the source of voltage.

Claim 25

Independent Claim 175 words

A method for programming a read-only memory cell, comprising the steps of: defining a cell at a face of a semiconductor layer to be of a first conductivity type; defining the placement of a pair of elongate spaced-apart parallel word line conductors to cross the cell, a first potential channel region associated with a first of the word line conductors, a second potential channel region associated with a second of the word line conductors; deselecting one of the potential channel regions by forming a thick insulator layer thereacross; selecting a remaining one of the potential channel regions by not forming the thick insulator layer thereacross; growing a gate insulator layer on the face; forming the word line conductor pair according to their defined placement; and implanting exposed areas of the cell with a dopant of the second conductivity type using the thick insulator layer and the one of said word line conductors not associated with the thick insulator layer as a mask, such that a transistor will be formed around the selected potential channel region.

Claim 26

Independent Claim 175 words

A method for programming a read-only memory cell, comprising the steps of: defining a cell at a face of a semiconductor layer to be of a first conductivity type; defining the placement of a pair of elongate spaced-apart parallel word line conductors to cross the cell, a first potential channel region associated with a first of the word line conductors, a second potential channel region associated with a second of the word line conductors; deselecting one of the potential channel regions by forming a thick insulator layer thereacross; selecting a remaining one of the potential channel regions by not forming the thick insulator layer thereacross; growing a gate insulator layer on the face; forming the word line conductor pair according to their defined placement; and implanting exposed areas of the cell with a dopant of the second conductivity type using the thick insulator layer and the one of said word line conductors not associated with the thick insulator layer as a mask, such that a transistor will be formed around the selected potential channel region.

Claim 27

Independent Claim 119 words

A method for programming an array of read-only memory cells, comprising the steps of: for each cell, coupling one end of a transistor of the cell to one of a plurality of bit line conductors of the array; in each cell representing a first logic state, forming a transistor current path between the transistor end and a first voltage source; in each cell representing a second logic state, forming a transistor current path between the transistor end and a second voltage source; and for each cell, forming a control electrode to control the conductance of the current path of the transistor; and coupling each of the control electrodes to one of a plurality of word lines of the array.

Claim 28

Independent Claim 119 words

A method for programming an array of read-only memory cells, comprising the steps of: for each cell, coupling one end of a transistor of the cell to one of a plurality of bit line conductors of the array; in each cell representing a first logic state, forming a transistor current path between the transistor end and a first voltage source; in each cell representing a second logic state, forming a transistor current path between the transistor end and a second voltage source; and for each cell, forming a control electrode to control the conductance of the current path of the transistor; and coupling each of the control electrodes to one of a plurality of word lines of the array.

Claim 29

Independent Claim 141 words

A method for programming a read-only memory cell, comprising the steps of: forming a first transistor such that one end of a current path thereof is coupled to a first voltage source representative of a first bit value; forming a second transistor such that a first end of a current path thereof is coupled to a second voltage source representative of a second bit value; coupling control electrodes of said first and second transistors to a word line for selectively rendering the current paths of said transistors conductive; and coupling a preselected, programmed one of a pair of second ends of respective current paths of said first and second transistors to a bit line, such that a preselected one of the first and second transistors selectively couples the bit line to a preselected one of the first and second voltage sources.

Claim 30

Independent Claim 141 words

A method for programming a read-only memory cell, comprising the steps of: forming a first transistor such that one end of a current path thereof is coupled to a first voltage source representative of a first bit value; forming a second transistor such that a first end of a current path thereof is coupled to a second voltage source representative of a second bit value; coupling control electrodes of said first and second transistors to a word line for selectively rendering the current paths of said transistors conductive; and coupling a preselected, programmed one of a pair of second ends of respective current paths of said first and second transistors to a bit line, such that a preselected one of the first and second transistors selectively couples the bit line to a preselected one of the first and second voltage sources.

Read-only memory cell and method of forming same

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