Data processing system

Claim 2

Data processing system having at least one processor and a common master storage (10) for reading data from and writing data to said processor (20), characterized by a combination of a cache storage unit (18) coupled to said processor and to the master storage for reading data from the common storage and from the processor (20), and for writing data to the processor; of a separate buffer storage unit (27) coupled to the processor and to the master storage for reading data directly from the processor in parallel with the cache storage unit coupled to said processor, and for writing data to the master storage; of a storage controller (12) coupled to said buffer storage unit for transferring said data in the buffer storage unit to the common storage.

Claim 3

Data processing system according to claim 1, characterized in that the buffer storage holds said data in at least one entry, the entry having a first portion specifying said data, and a second portion specifying an address in the master storage (10) for holding said data.

Claim 4

Data processing system according to claim 2, characterized in that the buffer storage unit contains a plurality of said entries in a predetermined order for holding said data, and that the storage controller (12) transfers said data from said entries into the master storage (10) in said predetermined order; that each of said entries further contains a status bit designating whether said data in its entry is to be stored sequentially with respect to data in another entry in said master storage (10); that each of said entries contains a status entity indicating a group of said entries belonging to the same instruction, and that the first portion is adapted to hold multiple units of said data.

Claim 5

Data processing system according to claim 2, characterized in that the second portion is adapted to hold both an effective address and an absolute address associated with said data in said data portion, and/or that the entry is further adapted to hold a plurality of status bits, identifying the association of said data with one of a current instruction and a previous instruction.

Claim 6

Data processing system according to claim 3, characterized in that each of said data units is individually writable to said master storage, and that said entry further contains a plurality of write flags designating which of said individual units is to be written to said master storage.

Claim 7

Data processing system according to claim 1 with multiple processors and a common master storage for reading data from and writing data to each of said processors, characterized by a combination of a set of cache storage units (18a-c) each coupled to one of said processors (20a-c) and to said master storage (10 a, b) for reading data from said common storage and from said one processor, and for writing data to said one processor; of a separate set of buffer storage units each coupled to one of said processors (20a-c) and to said master storage (10) for reading data directly from said one processor in parallel with said cache storage unit coupled to said one processor, and for writing data to said master storage; of a storage controller (26) coupled to all of said buffer storage units for transferring said data in said buffer storage units one at a time among said buffer storage units to said common storage.

Claim 8

Data processing system according to claim 6, characterized in that each of the buffer storage units contains a plurality of said entries each holding one item of said data along with a master-storage address associated with said item of data.

Claim 9

Data processing system according to claim 7, characterized by fetch-conflict resolving means for checking each said master-storage address in one of the buffer storage means against an address fetched by a corresponding one of the processors from the master storage, so as to prevent a fetch conflict between said one processor and another of said processors.