EP0375869A2
Expired / Lapsed
EP
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Monolithic semiconductor chip interconnection technique and arragement
Assignee: HP Inc
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Filing: 1989-10-20
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Granted: —
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Expires: 2009-10-20
Abstract
Abstract An interconnection arrangement (14) and technique for a single semiconductor chip (13) containing incomplete electric circuitry and having electric surface terminations (13˝) permitting said incomplete electric circuitry to be externally interconnected, the interconnection arrangement (14) being mountable on the semiconductor chip and capable of electrically communicating with the semiconductor chip through electric surface terminations (13˝,14˝) on the top surface (13′) of the semiconductor chip and on the bottom surface (14′) of the interconnection arrangement.
Inventors
- 👤 Ravindhar K. Kaw
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 03:32
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/67; H10W70/68; H10W70/685; H10W90/00; H10W90/701; H10W90/721; H10W90/724
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
121 words
An interconnection arrangement for a semiconductor chip containing at least a single incomplete electric circuit including electric terminations on its top surface, characterized by a plurality of means (14˝) for electrically communicating with a corresponding plurality of first electric terminations (13˝) of an incomplete electric circuit in a semiconductor chip (13) subject to interconnection; means (14) for supporting said plurality of means (14˝) for electrically communicating, in position for electric communication with the semiconductor chip (13) including a top surface (13′) and an incomplete electric circuit having a plurality of said first electrical terminations (13˝) fabricated in said top surface (13′); and means (16) for electrically interconnecting said plurality of means (14˝) for electrically communicating, whithin said means (14) for supporting.
Claim 2
Dependent Claim
121 words
An interconnection arrangement for a semiconductor chip containing at least a single incomplete electric circuit including electric terminations on its top surface, characterized by a plurality of means (14˝) for electrically communicating with a corresponding plurality of first electric terminations (13˝) of an incomplete electric circuit in a semiconductor chip (13) subject to interconnection; means (14) for supporting said plurality of means (14˝) for electrically communicating, in position for electric communication with the semiconductor chip (13) including a top surface (13′) and an incomplete electric circuit having a plurality of said first electrical terminations (13˝) fabricated in said top surface (13′); and means (16) for electrically interconnecting said plurality of means (14˝) for electrically communicating, whithin said means (14) for supporting.
Claim 3
Dependent Claim
56 words
The arrangement of claim 1, characterized in that said means for electric communication include a predetermined number of second electric surface terminations (14˝) for communicating with said first electric surface terminations (13˝) of the semiconductor chip (13); and means for interconnecting selected ones of said second electric surface terminations (14˝) of said means for electric communication.
Claim 4
Dependent Claim
34 words
The arrangement of claim 1 or 2, characterized by means for positioning said plurality of said second electric surface terminations (14˝) to enable joinder with a plurality of said first electric surface terminations (13˝).
Claim 5
Dependent Claim
14 words
The arrangement of claim 3, characterized in that said means for positioning includes silicon.
Claim 6
Dependent Claim
15 words
The arrangement of claim 3, characterized in that said means for positioning includes ceramic material.
Claim 7
Dependent Claim
24 words
The arrangement of one of the preceding claims, characterized in that said means for interconnecting includes conductive layers (142) separated by insulative material (141).
Claim 8
Dependent Claim
14 words
The arrangement of claim 6, characterized in that said conductive layers (142) are metallic.
Claim 9
Dependent Claim
18 words
The arrangement of claim 6, characterized in that at least one of said conductive layers (142) includes copper.
Claim 10
Dependent Claim
18 words
The arrangement of claim 6, characterized in that at least one of said conductive layers (142) include aluminum.
Claim 11
Dependent Claim
105 words
An interconnection method for a semiconductor chip (13) including a top surface (13′) and an incomplete electric circuit including first electric surface terminations (13˝) in said top surface, comprising the steps of: (a) manufacturing an interconnection arrangement (14) having a bottom surface (14′) including a plurality of second electric surface terminations (14˝) and defining a predetermined arrangement of electrically conductive paths between said second electric surface terminations, and (b) mounting said interconnection arrangement (14) upon the semiconductor chip to establish electric communication between selected ones of said first and second electric surface terminations (13˝,14˝), whereby said incomplete electric circuit achieves a desired electrical interconnection scheme.
Claim 12
Dependent Claim
105 words
An interconnection method for a semiconductor chip (13) including a top surface (13′) and an incomplete electric circuit including first electric surface terminations (13˝) in said top surface, comprising the steps of: (a) manufacturing an interconnection arrangement (14) having a bottom surface (14′) including a plurality of second electric surface terminations (14˝) and defining a predetermined arrangement of electrically conductive paths between said second electric surface terminations, and (b) mounting said interconnection arrangement (14) upon the semiconductor chip to establish electric communication between selected ones of said first and second electric surface terminations (13˝,14˝), whereby said incomplete electric circuit achieves a desired electrical interconnection scheme.
References Cited (Backward Citations)
No citation records indexed.
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