EP0374971A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Three-dimensionally stacked LSI
Assignee: Panasonic Holdings Corp
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Filing: 1989-12-23
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Granted: —
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Expires: 2009-12-23
Abstract
Abstract Disclosed is a three-dimensionally stacked LSI having a plurality of integrated-circuit layers stacked together, each of which is equipped with a plurality of circuit elements (2, 10, 16). Each of the circuit elements are equipped with a power terminal (4) of its own, which is connected through interlayer via-hole wiring (22) to the power wiring of the uppermost integrated-circuit layer. The power wiring of the uppermost integrated-circuit layer is formed of a metal exhibiting a low electrical resistance, for example, Al, whereas the metal wirings of the other layers, which are exposed to high temperatures when forming the upper layers, are formed of W.
Inventors
- 👤 Yasuhiro Tomita
- 👤 Yoshiyuki Takagi
- 👤 Shigenobu Akiyama
- 👤 Kenichi Yamazaki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 12:45
CPC Classifications
H; H10; H10D; H10D88/00; H10W; H10W20/00; H10W20/20; H10W20/40; H10W20/41; H10W20/427
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
52 words
A three-dimensionally stacked LSI comprising a plurality of integrated-circuit layers stacked together, each of said integrated-circuit layers being equipped with a plurality of circuit elements, said circuit elements being equipped with respective power terminals, which are connected through via-hole wiring between stacked layers to the power wiring of the uppermost integrated-circuit layer.
Claim 2
Dependent Claim
52 words
A three-dimensionally stacked LSI comprising a plurality of integrated-circuit layers stacked together, each of said integrated-circuit layers being equipped with a plurality of circuit elements, said circuit elements being equipped with respective power terminals, which are connected through via-hole wiring between stacked layers to the power wiring of the uppermost integrated-circuit layer.
Claim 3
Dependent Claim
73 words
A three-dimensionally stacked LSI as claimed in Claim 1, wherein the respective power terminals of said circuit elements in said plurality of integrated-circuit layers excluding those in the uppermost layer are arranged in such a manner that they are in alignment with one another as seen from above, the power terminals thus arranged in alignment being collectively connected through via-hole wiring between stacked layers to the power wiring of the uppermost integrated-circuit layer.
Claim 4
Dependent Claim
47 words
A three-dimensionally stacked LSI as claimed in Claim 1 or 2, wherein the wiring of the uppermost integrated-circuit layer is formed of aluminium, and the wiring of the lower integrated-circuit layers and the via-hole wiring between stacked layers are formed of a refractory material such as tungsten.
Claim 5
Dependent Claim
101 words
A three-dimensionally stacked LSI comprising: a semiconductor substrate; a plurality of semiconductor-integrated-circuit layers formed on the semiconductor substrate with interlayer insulators being arranged therebetween; a plurality of circuit elements formed in each of said integrated-circuit layer, said circuit elements being equipped with respective power terminals; via-hole wirings provided in via holes which are formed in those portions of said interlayer insulators and of said semiconductor integrated-circuit layers which correspond to predetermined power terminals of said circuit elements excluding those in the uppermost integrated-circuit layer; said via-hole wiring connecting said predetermined power terminals to power wiring formed on the uppermost integrated-circuit layer.
Claim 6
Dependent Claim
101 words
A three-dimensionally stacked LSI comprising: a semiconductor substrate; a plurality of semiconductor-integrated-circuit layers formed on the semiconductor substrate with interlayer insulators being arranged therebetween; a plurality of circuit elements formed in each of said integrated-circuit layer, said circuit elements being equipped with respective power terminals; via-hole wirings provided in via holes which are formed in those portions of said interlayer insulators and of said semiconductor integrated-circuit layers which correspond to predetermined power terminals of said circuit elements excluding those in the uppermost integrated-circuit layer; said via-hole wiring connecting said predetermined power terminals to power wiring formed on the uppermost integrated-circuit layer.
Claim 7
Dependent Claim
38 words
A three-dimensionally stacked LSI as claimed in anyone of claims 1 to 4, wherein the power wiring of the uppermost layer is formed of aluminum, said power terminals and said via-hole wiring being formed of a refractory material.
Claim 8
Dependent Claim
34 words
A three-dimensionally stacked LSI as claimed in anyone of Claims 1 to 5, wherein said semiconductor integrated-circuit layers consist of semiconductor layers which are prepared by annealing non-single-crystal semiconductor so as to crystallize it.
Claim 9
Dependent Claim
38 words
A three-dimensionally stacked LSI as claimed in anyone of claims 1 to 6, wherein power relay terminals are formed on the middle integrated-circuit layers, via-hole wiring being formed in those via-holes above and below these power relay terminals.
Claim 10
Dependent Claim
26 words
A three-dimensionally stacked LSI as claimed in anyone of Claims 1 to 7 wherein said via-hole wiring and said power wiring function as a heat sink.
References Cited (Backward Citations)
No citation records indexed.
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