Op branching for starting micro-routines

Claim 2

A computer having a processor which includes means for hardwired execution of macro­instructions, said processor further including means for microprogram execution of said macro­instructions in response to external control, said microprogram means including means for translating said macroinstructions into its associated microprogram routines comprising: a table maintained in a first storage means containing entries representing the origin of the microprogram routines, said first storage means accessed by an address generated from an op-code of said macroinstruction, a second storage means containing said micro­program routines and accessed by said entries from said table in said first storage means, said second storage means providing said microprogram routines to said processor, and a control means for switching between said hardwired execution means and said microprogram execution means, said control means connected to and responsive to said processor and first and second storage means.

Claim 3

A computer as in claim 1 where detection of hardwired and microprogrammed executed macro­instructions is made with the same logic wherein said logic generates only an address for a hardwired macroinstruction.

Claim 4

A computer as in claim 1 or 2 wherein said first storage means contains multiple randomly assessable tables.

Claim 5

A computer as in one of claims 1 to 3 wherein said second storage means address is taken from entries in said table and where address derivation and instruction setup is done by the hardware in parallel.

Claim 6

A computer having a processor which includes hardware and microprogram means for executing a normal and extended op-code macroinstruction, said microprogram means having translation means for translating said macroinstruction into its associated microprogram routines, said trans­lation means comprising: op-code break out means for maintaining at least one main resolution table embedded in random-­access-memory, said table having entries representing the origins of said microprogram routines and producing an output, when addressed by the op-code of said macroinstruction, a single level control storage means for main­taining said microprogram routines and connected to said op-code break out means, said single level control storage means accessed by said output of said resolution table, a hardware facility means for generating and maintaining setup and initialization information for said macroinstruction, said facility means connected to said op-code break out means and said control storage means and capable of being altered by said processor in normal operation, and control means for switching between said hardware and microprogram means, said control means connected to and responsive to said hardware facility, said single level control storage means and said op-code break out means.

Claim 7

A computer having a processor which includes hardware and microprogram means for executing a normal and extended op-code macroinstruction, said microprogram means having translation means for translating said macroinstruction into its associated microprogram routines, said trans­lation means comprising: op-code break out means for maintaining at least one main resolution table embedded in random-­access-memory, said table having entries representing the origins of said microprogram routines and producing an output, when addressed by the op-code of said macroinstruction, a single level control storage means for main­taining said microprogram routines and connected to said op-code break out means, said single level control storage means accessed by said output of said resolution table, a hardware facility means for generating and maintaining setup and initialization information for said macroinstruction, said facility means connected to said op-code break out means and said control storage means and capable of being altered by said processor in normal operation, and control means for switching between said hardware and microprogram means, said control means connected to and responsive to said hardware facility, said single level control storage means and said op-code break out means.

Claim 8

A computer as in claim 5 wherein said op-code break out means includes special resolution tables for execution of said extended op-code macroinstructions.

Claim 9

A computer as in claim 5 or 6 wherein entries in said main resolution table allows a hardwired macroinstruction to be executed by microprogram.

Claim 10

A computer as in one of claims 5 to 7 wherein the op-code bits of said extended op-code macro­instruction are greater then those in a normal op-code macroinstruction.

Claim 11

A computer as in one of claims 5 to 8 wherein the hardware facility means includes registers, latches and stacks capable of processor alteration in normal operation.

Claim 14

A method for translating a macroinstruction of claim 10, wherein said table includes a special table for resolution of an extended op-code macroinstruction to eliminate the need for microprogram routine resolution.

Claim 15

A method for translating a macroinstruction of claim 10 or 11, wherein said facility is setup by hardware so that said microprogram routine will not need to assemble data.