MOS type field effect transistor formed on a semiconductor layer on an insulator substrate

Claim 2

A SOI-MOSFET comprising in combination, source and drain regions (7, 7a; 8, 8a) formed of respective impurity regions of a first type in a thin semiconductor layer (3) deposited not more than 1500Å in thickness on an insulator (2), a channel region (6) having a predetermined impurity concentration of a second type in said thin semiconductor layer (6) between said source region (7, 7a) and said drain region (8, 8a), a gate electrode (5) positioned adjacent said channel region (6) and separated from said semiconductor layer (3) by an insulator layer (4) deposited on said semiconductor layer (3), and at least one carrier storage region (9a, 9b) having an impurity concentration of the second type higher than the impurity concentration of said channel region (6) whereby excess carriers of the second type are removed from said channel region (6) into said carrier storage region (9a, 9b).

Claim 3

A SOI-MOSFET according to claim 1, wherein said carrier storage region (9a, 9b) are formed in said semiconductor layer (3) in contact with at least a portion of the bottom of said channel region (6) and with at least a portion of the bottom of said source region (7, 7a).

Claim 4

A SOI-MOSFET according to claim 2, further comprising a second carrier storage region (10a, 10b) formed in said semiconductor layer (3) in contact with at least a portion of the bottom of said channel region (6) and with at least a portion of the bottom of said drain regions (8, 8a).

Claim 5

A SOI-MOSFET according to claim 2, further comprising a metal silicide layer (20a) formed on said source region (7) and having a non-uniform depth, said silicide layer (20a) being of such a depths that said layer is passed locally through said source region (7) to reach said carrier storage region (9a).

Claim 6

A SOI-MOSFET according to claim 2, further comprising an aluminum layer (21a) formed on said source region (7), said aluminum layer including alloy spikes locally passing through said source region (7) to reach said carrier storage region (9a).

Claim 7

A SOI-MOSFET comprising in combination, source and drain regions (7, 7a; 8, 8a) formed of respective impurity regions of a first type in a thin semiconductor layer (3) deposited not more than 1500Å in thickness on an insulator (2), said drain region (8, 8a) including a lightly doped drain (8a), a channel region (6) having a predetermined impurity concentration of a second type in said thin semiconductor layer (6) between said source region (7, 7a) and said drain region (8, 8a), a gate electrode (5) positioned adjacent said channel region (6) and separated from said semiconductor layer (3) by an insulator layer (4) deposited on said semiconductor layer (3), and at least one carrier storage region (9a, 9b) having an impurity concentration of the second type higher than the impurity concentration of said channel region (6) whereby excess carriers of the second type are removed from said channel region (6) into said carrier storage region (9a, 9b).

Claim 8

A SOI-MOSFET comprising in combination, source and drain regions (7, 7a; 8, 8a) formed of respective impurity regions of a first type in a thin semiconductor layer (3) deposited not more than 1500Å in thickness on an insulator (2), said drain region (8, 8a) including a lightly doped drain (8a), a channel region (6) having a predetermined impurity concentration of a second type in said thin semiconductor layer (6) between said source region (7, 7a) and said drain region (8, 8a), a gate electrode (5) positioned adjacent said channel region (6) and separated from said semiconductor layer (3) by an insulator layer (4) deposited on said semiconductor layer (3), and at least one carrier storage region (9a, 9b) having an impurity concentration of the second type higher than the impurity concentration of said channel region (6) whereby excess carriers of the second type are removed from said channel region (6) into said carrier storage region (9a, 9b).

Claim 9

A SOI-MOSFET according to claim 6, wherein said source region (7, 7a) includes a lightly doped source (7a).

Claim 10

A SOI-MOSFET according to claim 7, wherein said carrier storage region (9b) is formed beneath said lightly doped source (7a).

Claim 11

A SOI-MOSFET according to claim 8, further comprising a second carrier storage region (10b) formed beneath said lightly doped drain (8a).

Claim 12

A SOI-MOSFET comprising in combination, source and drain regions (7, 7a; 8, 8a) formed of respective impurity regions of a first type in a thin semiconductor layer (3) deposited not more than 1500Å in thickness on an insulator (2), a channel region (6) having a predetermined impurity concentration of a second type in said thin semiconductor layer (6) between said source region (7, 7a) and said drain region (8, 8a), a gate electrode (5) positioned adjacent said channel region (6) and separated from said semiconductor layer (3) by an insulator layer (4) deposited on said semiconductor layer (3), and a crystal defect region (9c) having crystal defects whereby excess carriers of the second type are removed from said channel region (6) into said crystal defect region (9c).

Claim 13

A SOI-MOSFET comprising in combination, source and drain regions (7, 7a; 8, 8a) formed of respective impurity regions of a first type in a thin semiconductor layer (3) deposited not more than 1500Å in thickness on an insulator (2), a channel region (6) having a predetermined impurity concentration of a second type in said thin semiconductor layer (6) between said source region (7, 7a) and said drain region (8, 8a), a gate electrode (5) positioned adjacent said channel region (6) and separated from said semiconductor layer (3) by an insulator layer (4) deposited on said semiconductor layer (3), and a crystal defect region (9c) having crystal defects whereby excess carriers of the second type are removed from said channel region (6) into said crystal defect region (9c).

Claim 14

A SOI-MOSFET according to claim 10, wherein said crystal defect region (9c) is formed in at least said channel region (6) at a lower layer portion in the vicinity of said source region (7, 7a).

Claim 15

A SOI-MOSFET according to claim 11, wherein said crystal defect region (9c) extend into a lower layer portion of said source region (7, 7a).

Claim 16

A MOSFET having: a source (7); a drain (8); and a channel-forming region (6) extending therebetween; characterised by: carrier sink means (9a; 9b; 9c) disposed adjacent to both the channel-forming region (6) and the source (7), and being so arranged for receiving excess carriers, which excess carriers would in the absence of said carrier sink means reduce source to drain withstand voltage.

Claim 17

A MOSFET having: a source (7); a drain (8); and a channel-forming region (6) extending therebetween; characterised by: carrier sink means (9a; 9b; 9c) disposed adjacent to both the channel-forming region (6) and the source (7), and being so arranged for receiving excess carriers, which excess carriers would in the absence of said carrier sink means reduce source to drain withstand voltage.

Claim 18

A MOSFET, as claimed in claim 13, wherein the source (7), the drain (8), and the channel-forming region (6), are formed in a single semiconductor layer (3) that is supported upon the surface of an insulator (1).

Claim 19

A MOSFET, as claimed in claim 14, wherein said single semiconductor layer (3) is sufficiently thin that said channel-forming region (6) is fully depletable, the entirety thereof thus providing in use a source-to-drain channel of the MOSFET.