Self latching logic gate

Claim 2

A self-latching logic gate comprising: first logic gate means for generating an output signal representative of a function of two or more input signals including a logic gate having at least two transistors each transistor having first, second and third terminals, said first terminals of each transistor being connected to provide an output terminal of said logic gate means and said self-­latching logic gate, said second terminals of said transistors providing first and second data input terminals for said logic gate means, and said third terminals of each transistor being connected to a common termination; first and second complementary mode transistors, each transistor having first, second and third terminals, said first terminal of said first transistor being connected to a source of electrical potential, said second terminals of said first and said second transistors being connected to each other to provide a common input terminal for said first and second transistors, said third terminal of said first transistor being connected to said output terminal of said first logic gate, said first terminal of said second transistor being connected to said output terminal of said first logic gate, and said third terminal of said second transistor being connected to said common termination; and second logic gate means for generating an output signal representative of a function of two or more input signals, said second logic gate means including a second logic gate having first and second inputs terminals, said first input terminal being connected to said output terminal of said first logic gate means, said second input terminal providing a latch input terminal for said self-latching gate, and the output terminal of said second logic gate being connected to the common input terminal of said first and second transistors.

Claim 3

A programmable logic array comprising: array logic means for providing product terms on selected lines on receipt of an input signal; latch means for providing a logic function of said product terms and for latching the result of said logic function, said latch means including a self-latching logic gate comprising: first logic gate means for generating an output signal representative of a function of two or more input signals including a logic gate having at least two transistors each transistor having first, second and third terminals, said first terminals of each transistor being connected to provide an output terminal of said logic gate means, said second terminals of said transistors providing first and second data input terminals for said logic gate means, and said third terminals of each transistor being connected to a common termination; first and second complementary mode transistors, each transistor having first, second and third terminals, said first terminal being connected to a source of electrical potential, said second terminals of said first and said second transistors being connected to each other to provide a common input terminal for said first and second transistors, said third terminal of said first transistor being connected to said output terminal of said logic gate, said first terminal of said second transistor being connected to said output terminal of said logic gate, and said third terminal of said second transistor being connected to said common termination; and second logic gate means for generating an output signal representative of a function of two or more input signals, said second logic gate means including a second logic gate having first and second inputs terminals, said first input terminal being connected to said output terminal of said first logic gate means, said second input terminal providing a latch input terminal for said self-latching gate, and the output terminal of said second logic gate being connected to the common input terminal of said first and second transistors.

Claim 4

A programmable logic array comprising: array logic means for providing product terms on selected lines on receipt of an input signal; latch means for providing a logic function of said product terms and for latching the result of said logic function, said latch means including a self-latching logic gate comprising: first logic gate means for generating an output signal representative of a function of two or more input signals including a logic gate having at least two transistors each transistor having first, second and third terminals, said first terminals of each transistor being connected to provide an output terminal of said logic gate means, said second terminals of said transistors providing first and second data input terminals for said logic gate means, and said third terminals of each transistor being connected to a common termination; first and second complementary mode transistors, each transistor having first, second and third terminals, said first terminal being connected to a source of electrical potential, said second terminals of said first and said second transistors being connected to each other to provide a common input terminal for said first and second transistors, said third terminal of said first transistor being connected to said output terminal of said logic gate, said first terminal of said second transistor being connected to said output terminal of said logic gate, and said third terminal of said second transistor being connected to said common termination; and second logic gate means for generating an output signal representative of a function of two or more input signals, said second logic gate means including a second logic gate having first and second inputs terminals, said first input terminal being connected to said output terminal of said first logic gate means, said second input terminal providing a latch input terminal for said self-latching gate, and the output terminal of said second logic gate being connected to the common input terminal of said first and second transistors.

Claim 5

A programmable logic array comprising: input pad means for providing a plurality of input signals; input buffer means, connected to said input pad means, for detecting a change in a signal provided to said input pad means and for generating a first output signal in response thereto; pulse generating means for generating a pulse in response to said first output signal; array logic means for providing product terms on receipt of said pulse; sense amplifier means, responsive to said pulse, for detecting predetermined signals provided by array logic means; latch block means for providing a logic function of said product terms on command from said sense amplifier means and for latching the result of said logic function, said latch block means including a self-­latching logic gate comprising: first logic gate means for generating an output signal representative of a function of two or more input signals including a logic gate having at least two transistors each transistor having first, second and third terminals, said first terminals of each transistor being connected to provide an output terminal of said logic gate means, said second terminals of said transistors providing first and second data input terminals for said logic gate means, and said third terminals of each transistor being connected to a common termination; first and second complementary mode transistors, each transistor having first, second and third terminals, said first terminal being connected to a source of electrical potential, said second terminals of said first and said second transistors being connected to each other to provide a common input terminal f or said first and second transistors, said third terminal of said first transistor being connected to said output terminal of said logic gate, said first terminal of said second transistor being connected to said output terminal of said logic gate, and said third terminal of said second transistor being connected to said common termination; and second logic gate means for generating an output signal representative of a function of two or more input signals, said second logic gate means including a second logic gate having first and second inputs terminals, said first input terminal being connected to said output terminal of said first logic gate means, said second input terminal providing a latch input terminal for said self-latching gate, and the output terminal of said second logic gate being connected to the common input terminal of said first and second transistors; macrocell means for providing a predetermined function in response to the output of said latch block means; and output pad means for outputting a result of said predetermined function.

Claim 6

A programmable logic array comprising: input pad means for providing a plurality of input signals; input buffer means, connected to said input pad means, for detecting a change in a signal provided to said input pad means and for generating a first output signal in response thereto; pulse generating means for generating a pulse in response to said first output signal; array logic means for providing product terms on receipt of said pulse; sense amplifier means, responsive to said pulse, for detecting predetermined signals provided by array logic means; latch block means for providing a logic function of said product terms on command from said sense amplifier means and for latching the result of said logic function, said latch block means including a self-­latching logic gate comprising: first logic gate means for generating an output signal representative of a function of two or more input signals including a logic gate having at least two transistors each transistor having first, second and third terminals, said first terminals of each transistor being connected to provide an output terminal of said logic gate means, said second terminals of said transistors providing first and second data input terminals for said logic gate means, and said third terminals of each transistor being connected to a common termination; first and second complementary mode transistors, each transistor having first, second and third terminals, said first terminal being connected to a source of electrical potential, said second terminals of said first and said second transistors being connected to each other to provide a common input terminal f or said first and second transistors, said third terminal of said first transistor being connected to said output terminal of said logic gate, said first terminal of said second transistor being connected to said output terminal of said logic gate, and said third terminal of said second transistor being connected to said common termination; and second logic gate means for generating an output signal representative of a function of two or more input signals, said second logic gate means including a second logic gate having first and second inputs terminals, said first input terminal being connected to said output terminal of said first logic gate means, said second input terminal providing a latch input terminal for said self-latching gate, and the output terminal of said second logic gate being connected to the common input terminal of said first and second transistors; macrocell means for providing a predetermined function in response to the output of said latch block means; and output pad means for outputting a result of said predetermined function.

Claim 7

In a macrocell having a register with first and second input paths, said first input path including an inverter, and first and second switches in each path respectively, polarity option control logic comprising: first logic means for receiving a clock input and a polarity input signal and controlling the activation of said first switch in response thereto and second logic means for receiving said clock input and said polarity input signal inverted and controlling the activation of said second switch in response thereto; whereby when said polarity input signal is in a first state, said first input path is enabled via said first switch in accordance with said clock signal and when said polarity input signal is in a second state, said second input path is enabled via said second switch in accordance with said clock signal.

Claim 8

In a macrocell having a register with first and second input paths, said first input path including an inverter, and first and second switches in each path respectively, polarity option control logic comprising: first logic means for receiving a clock input and a polarity input signal and controlling the activation of said first switch in response thereto and second logic means for receiving said clock input and said polarity input signal inverted and controlling the activation of said second switch in response thereto; whereby when said polarity input signal is in a first state, said first input path is enabled via said first switch in accordance with said clock signal and when said polarity input signal is in a second state, said second input path is enabled via said second switch in accordance with said clock signal.

Claim 9

An initialization circuit comprising: latch means for providing a first stable output state prior to the application of power thereto and a second stable output state after the application of power thereto, said latch means having an input terminal, an output terminal and first and second power terminals, said first power terminal being connected to a source of electrical potential and said second power terminal being connected to a common termination and first switching means for applying a state switching input signal to said input terminal of said latch means at some time after the application of power thereto, said first switching means including a first switching element having first, second and third terminals, said first terminal being an output terminal and being connected to said input terminal of said latch means, said second terminal being an input terminal and being connected to a source of electrical potential, and said third terminal being connected to a common termination.

Claim 10

An initialization circuit comprising: latch means for providing a first stable output state prior to the application of power thereto and a second stable output state after the application of power thereto, said latch means having an input terminal, an output terminal and first and second power terminals, said first power terminal being connected to a source of electrical potential and said second power terminal being connected to a common termination and first switching means for applying a state switching input signal to said input terminal of said latch means at some time after the application of power thereto, said first switching means including a first switching element having first, second and third terminals, said first terminal being an output terminal and being connected to said input terminal of said latch means, said second terminal being an input terminal and being connected to a source of electrical potential, and said third terminal being connected to a common termination.

Claim 11

An initialization circuit comprising: latch means for providing a first stable output state prior to the application of power thereto and a second stable output state after the application of power thereto, said latch means having an input terminal, an output terminal and first and second power terminals, said first power terminal being connected to a source of electrical potential and said second power terminal being connected to a common termination, said latch means including: a latch having an input terminal connected to the input terminal of said latch means and an output terminal connected to the output terminal of said latch means; a pull up capacitor connected between the input terminal of said latch and said source of electrical potential; and a pull down capacitor connected between the output of said latch and said common termination; and first switching means for applying a state switching input signal to said input terminal of said latch means at some time after the application of power thereto, said first switching means including: a first switching element having first, second and third terminals, said first terminal being an output terminal and being connected to said input terminal of said latch means, said second terminal being an input terminal and being connected to a source of electrical potential, and said third terminal being connected to a common termination and a delay capacitor connected between the input terminal of said first switching element and said common ground termination.

Claim 12

An initialization circuit comprising: latch means for providing a first stable output state prior to the application of power thereto and a second stable output state after the application of power thereto, said latch means having an input terminal, an output terminal and first and second power terminals, said first power terminal being connected to a source of electrical potential and said second power terminal being connected to a common termination, said latch means including: a latch having an input terminal connected to the input terminal of said latch means and an output terminal connected to the output terminal of said latch means; a pull up capacitor connected between the input terminal of said latch and said source of electrical potential; and a pull down capacitor connected between the output of said latch and said common termination; and first switching means for applying a state switching input signal to said input terminal of said latch means at some time after the application of power thereto, said first switching means including: a first switching element having first, second and third terminals, said first terminal being an output terminal and being connected to said input terminal of said latch means, said second terminal being an input terminal and being connected to a source of electrical potential, and said third terminal being connected to a common termination and a delay capacitor connected between the input terminal of said first switching element and said common ground termination.

Claim 13

An initialization circuit comprising: latch means for providing a first stable output state prior to the application of power thereto and a second stable output state after the application of power thereto, said latch means having an input terminal, an output terminal and first and second power terminals, said first power terminal being connected to a source of electrical potential and said second power terminal being connected to a common termination, said latch means including: a complementary metallic oxide semiconductor latch having an input terminal connected to the input terminal of said latch means and an output terminal connected to the output terminal of said latch means, a pull up capacitor connected between the input terminal of said latch and said source of electrical potential, and a pull down capacitor connected between the output of said latch and said common termination; and first switching means for applying a state switching input signal to said input terminal of said latch means at some time after the application of power thereto, said first switching means including: a first switching element having first, second and third terminals, said first terminal being an output terminal and being connected to said input terminal of said latch means, said second terminal being an input terminal and being connected to a source of electrical potential, and said third terminal being connected to a common termination and a delay capacitor connected between the input terminal of said first switching element and said common ground termination; input thresholding means connected between said source of electrical potential and said input terminal of said first switching element for applying the potential from said source to said input terminal of said first switching element when said potential exceeds a predetermined threshold; first fast recovery means connected to the input terminal of said first switching element for discharging any residual potential stored between the input terminal thereof and said common termination whenever the potential of said source of electrical potential drops below a predetermined level; and isolation means for connecting the output of said latch to a bus and for isolating said bus from said output of said latch.

Claim 14

An initialization circuit comprising: latch means for providing a first stable output state prior to the application of power thereto and a second stable output state after the application of power thereto, said latch means having an input terminal, an output terminal and first and second power terminals, said first power terminal being connected to a source of electrical potential and said second power terminal being connected to a common termination, said latch means including: a complementary metallic oxide semiconductor latch having an input terminal connected to the input terminal of said latch means and an output terminal connected to the output terminal of said latch means, a pull up capacitor connected between the input terminal of said latch and said source of electrical potential, and a pull down capacitor connected between the output of said latch and said common termination; and first switching means for applying a state switching input signal to said input terminal of said latch means at some time after the application of power thereto, said first switching means including: a first switching element having first, second and third terminals, said first terminal being an output terminal and being connected to said input terminal of said latch means, said second terminal being an input terminal and being connected to a source of electrical potential, and said third terminal being connected to a common termination and a delay capacitor connected between the input terminal of said first switching element and said common ground termination; input thresholding means connected between said source of electrical potential and said input terminal of said first switching element for applying the potential from said source to said input terminal of said first switching element when said potential exceeds a predetermined threshold; first fast recovery means connected to the input terminal of said first switching element for discharging any residual potential stored between the input terminal thereof and said common termination whenever the potential of said source of electrical potential drops below a predetermined level; and isolation means for connecting the output of said latch to a bus and for isolating said bus from said output of said latch.