EP0373768A2
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Digital frequency divider
Assignee: MagnaChip Semiconductor Ltd
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Filing: 1989-11-15
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Granted: —
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Expires: 2009-11-15
Abstract
Abstract A digital frequency divider capable of providing output pulses of frequency f out related by Y/X to the frequency of the input pulses f in , where X and Y are positive whole numbers and 0 < Y/X < 1 is particularly suited for high frequency digital applications. The X and Y values are stored in latches (2,3). An adder (6) receives the value Y and the value -X or 0, such that Y or Y-X is provided to a further adder (7) which receives a feedback signal from a flip-flop block (8). An AND gate (9) controlled in dependence on the sign of the number in the flip-flop block (8) to selectively pass input pulses f in to provide the output pulses f out .
Inventors
- 👤 Luke A. Perkins
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 17:54
CPC Classifications
H; H03; H03K; H03K21/00; G; G06; G06F; G06F7/00; G06F7/60; G06F7/68; H03K23/00; H03K23/64; H03K23/68
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
147 words
A digital frequency divider for receiving pulses at an input frequency f in and providing pulses at an output frequency f out , where f out = Y/X f in , characterized by; first adder means (4,6) adapted to provide the numerical value of Y or the difference between Y and X; second adder means (7) adapted to derive the difference between the number provided by said first adder means (4,6) and a stored number; storage means (8) adapted to successively store the difference derived by said second adder means (7) and to provide that difference as a stored number to said second adder means (7) during a subsequent derivation of a difference in said second adder means (7), operable at a rate derived from f in ; and output means (9) adapted to generate f out pulses depending upon the contents of said storage means (8).
Claim 2
Dependent Claim
147 words
A digital frequency divider for receiving pulses at an input frequency f in and providing pulses at an output frequency f out , where f out = Y/X f in , characterized by; first adder means (4,6) adapted to provide the numerical value of Y or the difference between Y and X; second adder means (7) adapted to derive the difference between the number provided by said first adder means (4,6) and a stored number; storage means (8) adapted to successively store the difference derived by said second adder means (7) and to provide that difference as a stored number to said second adder means (7) during a subsequent derivation of a difference in said second adder means (7), operable at a rate derived from f in ; and output means (9) adapted to generate f out pulses depending upon the contents of said storage means (8).
Claim 3
Dependent Claim
24 words
A digital frequency divider according to claim 1, characterized in that X and Y are positive whole numbers, with 0 < Y/X < 1.
Claim 4
Dependent Claim
31 words
A digital frequency divider according to :claim 2 characterized in that X and Y are binary form numerical values; and in that said second adder means (7) is a binary adder.
Claim 5
Dependent Claim
78 words
A digital frequency divider according to claim 3, characterized in that said first adder means (4,6) includes: a multiplexer (4) adapted to receive the value -X and to provide an output of the value -X or 0, and a binary adder (6) adapted to receive the output of said multiplexer (4) and the value Y; and in that said multiplexer (4) is controlled by a signal representing the sign of the numbers stored in said storage means (8).
Claim 6
Dependent Claim
26 words
A digital frequency divider according to claim 4, characterized in that the X value is provided to said multiplexer (4) as a 2's complement negative value.
Claim 7
Dependent Claim
38 words
A digital frequency divider according to claim 5, characterized in that said output means (9) is a gate which blocks or passes f in pulses depending upon the sign of the number stored in said storage means (8).
Claim 8
Dependent Claim
22 words
A digital frequency divider according to claim 1, characterized in that said storage means (8) is a clocked numerical value latching device.
Claim 9
Dependent Claim
34 words
A digital frequency divider according to claim 7, characterized in that said clocked numerical value latching device (8) is a D-type flip-flop register synchronized to the falling edges of the received f in pulses.
References Cited (Backward Citations)
No citation records indexed.
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