EP0373672A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory circuit having an improved restoring control circuit
Assignee: NEC Corp
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Filing: 1989-12-15
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Granted: —
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Expires: 2009-12-15
Abstract
Abstract A dynamic memory circuit which can operate with a reduced amount of current noise and without destruction of stored data is disclosed. The memory circuit includes dynamic memory cells necessitating restoring operation, a read circuit for performing a read-out operation in an active state and a restore circuit for performing a restore operation in a reset state following the active state.
Inventors
- 👤 Takeo Fujii
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 23:22
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4094; G11C11/408; G11C11/4085; G11C11/4097
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
88 words
A semiconductor memory circuit comprising a plurality of dynamic type memory cells which necessitate restoring of read-out data for continuing storage of data, means for receiving an external control signal having an active level and an inactive level, means for operatively reading data from a selected memory cell in response to the active level of said external control signal and means for operatively restoring the data read from said selected memory cell into said selected memory cell in response to the inactive level of said external control signal.
Claim 2
Dependent Claim
88 words
A semiconductor memory circuit comprising a plurality of dynamic type memory cells which necessitate restoring of read-out data for continuing storage of data, means for receiving an external control signal having an active level and an inactive level, means for operatively reading data from a selected memory cell in response to the active level of said external control signal and means for operatively restoring the data read from said selected memory cell into said selected memory cell in response to the inactive level of said external control signal.
Claim 3
Dependent Claim
83 words
The memory circuit according to claim 1, further comprising a plurality of word lines coupled to said memory cells, means for selecting one of said word lines in response to the active level of said external control signal, a plurality of bit lines coupled to said memory cells, a plurality of sense amplifiers coupled to said bit lines, a first reference voltage wiring coupled to said sense amplifiers, and a second reference voltage wiring coupled to said selecting means and said reading means.
Claim 4
Dependent Claim
23 words
The memory circuit according to claim 1, in which each of said memory cells includes a storage capacitor and a transfer gate transistor.
Claim 5
Dependent Claim
27 words
The memory circuit according to claim 1, in which said reading means includes a common data line, and an output circuit coupled to said common data line.
Claim 6
Dependent Claim
48 words
The memory circuit according to claim 1, further comprising a plurality of bit lines coupled to said memory cells, each of said bit lines being divided into first and second segments, and a plurality of transfer gates inserted between the first and second segments of said bit lines.
References Cited (Backward Citations)
No citation records indexed.
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