EP0373631A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
MOS transistor and differential amplifier circuit with low offset
Assignee: Toshiba Corp
•
Filing: 1989-12-13
•
Granted: —
•
Expires: 2009-12-13
Abstract
Abstract A MOS transistor includes a gate electrode layer (35) formed on an insulation layer (34) which is formed on an element formation region defined by a field insulation layer (31) formed on a P-type semiconductor substrate (30). The gate electrode layer (35) has first and second openings (36a, 36b) formed therein. Further, N-type impurity diffusion regions (37a, 37b) acting as the drain and source of the MOS transistor are formed in those portions of the surface area of the semiconductor substrate (30) which lie under the first and second openings (36a, 36b).
Inventors
- 👤 Kenji C/O Intellectual Property Division Matsuo
- 👤 Yasukazu C/O Intellectual Property Division Noine
- 👤 Kazuhiko C/O Intellectual Property Division Kasai
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 13:56
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/519; H10D1/00; H10D1/40; H10D30/00; H10D30/60; H10D62/00; H10D62/10; H10D62/17
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
113 words
A MOS transistor formed in an element formation region (33; 43) defined by a field insulation layer (31; 41) formed on a semiconductor substrate (30; 40) of a first conductivity type, characterized by comprising: a gate electrode layer (35; 45) having first and second openings (36a, 36b; 46a, 46b) and formed on an insulation layer (34; 44) which is formed on said element formation region (33; 43); and first and second impurity diffusion layers (37a, 37b) of a second conductivity type respectively acting as a drain and a source and formed in those portions of the surface area of said semiconductor substrate (30) which lie under said first and second openings (36a, 36b).
Claim 2
Dependent Claim
113 words
A MOS transistor formed in an element formation region (33; 43) defined by a field insulation layer (31; 41) formed on a semiconductor substrate (30; 40) of a first conductivity type, characterized by comprising: a gate electrode layer (35; 45) having first and second openings (36a, 36b; 46a, 46b) and formed on an insulation layer (34; 44) which is formed on said element formation region (33; 43); and first and second impurity diffusion layers (37a, 37b) of a second conductivity type respectively acting as a drain and a source and formed in those portions of the surface area of said semiconductor substrate (30) which lie under said first and second openings (36a, 36b).
Claim 3
Dependent Claim
22 words
A MOS transistor according to claim 1, characterized in that said first and second openings (36a, 36b) have the same rectangular shape.
Claim 4
Dependent Claim
68 words
A MOS transistor according to claim 1, characterized in that said gate electrode layer (35) further has a third opening (36c) formed therein and said MOS transistor further includes a third impurity diffusion region (37c) of the second conductivity type formed in that portion of the surface area of said semiconductor substrate (30) which lies under said third opening (36c) to act as a source or drain region.
Claim 5
Dependent Claim
23 words
A MOS transistor according to claim 3, characterized in that said first to third openings (36a, 36b, 36c) have the same rectangular shape.
Claim 6
Dependent Claim
24 words
A MOS transistor according to claim 3, characterized in that said first to third openings (36a, 36b, 36c) are arranged along a first direction.
Claim 7
Dependent Claim
75 words
A MOS transistor according to claim 1, characterized in that said gate electrode layer (45) further has third and fourth openings (46c, 46d) formed therein and said MOS transistor further includes third and fourth impurity diffusion regions (47c, 47d) of the second conductivity type formed in those portions of the surface area of said semiconductor substrate (30) which lie under said third and fourth openings (46c, 46d) to respectively act as drain and source regions.
Claim 8
Dependent Claim
23 words
A MOS transistor according to claim 6, characterized in that said first to fourth openings (46a, 46b, 46c, 46d) have same rectangular shape.
Claim 9
Dependent Claim
37 words
A MOS transistor according to claim 3, characterized in that said first and second openings (46a, 46b) are arranged along a first direction and said third and fourth openings (46c, 46d) are parallel with said first direction.
Claim 10
Dependent Claim
139 words
A differential amplifier circuit comprising a pair of first and second differential transistors (Q1, Q3) having gates respectively supplied with first and second input signals, characterized in that each of said first and second differential transistors (Q1, Q3) comprising: a gate electrode layer (35; 45) having first and second openings (36a, 36b; 46a, 46b) and formed on an insulation layer (34; 44) which is formed on an element formation region (33; 43) defined on a semiconductor substrate (30; 40) by a field insulation layer (31; 41) formed on said semiconductor substrate (30; 40); and first and second impurity diffusion layers (37a, 37b) of a second conductivity type respectively acting as a drain and a source and formed in those portions of the surface area of said semiconductor substrate (30) which lie under said first and second openings (36a, 36b).
Claim 11
Dependent Claim
139 words
A differential amplifier circuit comprising a pair of first and second differential transistors (Q1, Q3) having gates respectively supplied with first and second input signals, characterized in that each of said first and second differential transistors (Q1, Q3) comprising: a gate electrode layer (35; 45) having first and second openings (36a, 36b; 46a, 46b) and formed on an insulation layer (34; 44) which is formed on an element formation region (33; 43) defined on a semiconductor substrate (30; 40) by a field insulation layer (31; 41) formed on said semiconductor substrate (30; 40); and first and second impurity diffusion layers (37a, 37b) of a second conductivity type respectively acting as a drain and a source and formed in those portions of the surface area of said semiconductor substrate (30) which lie under said first and second openings (36a, 36b).
Claim 12
Dependent Claim
23 words
A differential amplifier circuit according to claim 9, characterized in that said first and second openings (36a, 36b) have the same rectangular shape.
Claim 13
Dependent Claim
69 words
A differential amplifier circuit according to claim 9, characterized in that said gate electrode layer (35) further has a third opening (36c) formed therein and said MOS transistor further includes a third impurity diffusion region (37c) of the second conductivity type formed in that portion of the surface area of said semiconductor substrate (30) which lies under said third opening (36c) to act as a source or drain region.
Claim 14
Dependent Claim
24 words
A differential amplifier circuit according to claim 11, characterized in that said first to third openings (36a, 36b, 36c) have the same rectangular shape.
Claim 15
Dependent Claim
25 words
A differential amplifier circuit according to claim 11, characterized in that said first to third openings (36a, 36b, 36c) are arranged along a first direction.
Claim 16
Dependent Claim
76 words
A differential amplifier circuit according to claim 9, characterized in that said gate electrode layer (45) further has third and fourth openings (46c, 46d) formed therein and said MOS transistor further includes third and fourth impurity diffusion regions (47c, 47d) of the second conductivity type formed in those portions of the surface area of said semiconductor substrate (30) which lie under said third and fourth openings (46c, 46d) to respectively act as drain and source regions.
Claim 17
Dependent Claim
27 words
A differential amplifier circuit according to claim 14, characterized in that said first to fourth openings (46a, 46b, 46c, 46d) are formed with the same rectangular shape.
Claim 18
Dependent Claim
40 words
A differential amplifier circuit according to claim 14, characterized in that said first and second openings (46a, 46b) are arranged along a first direction and said third and fourth openings (46c, 46d) are formed in parallel with said first direction.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.