EP0371663A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Integrated circuit output buffer having improved ESD protection
Assignee: AT&T Inc
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Filing: 1989-11-16
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Granted: —
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Expires: 2009-11-16
Abstract
Abstract Improved electrostatic discharge (ESD) protection is obtained for an integrated circuit output buffer by connecting it to a bondpad (17) through a resistor (14). In one embodiment, the resistor (14′) is in the drain lead of the n-channel transistor (12). In a preferred embodiment, the n-channel pull- down device (403... 405) is connected to the bondpad (410) with multiple resistors (406 ... 408). The resistors may be formed in a deposited conductor level, typically silicide or doped polysilicon. The bondpad also has over- voltage clamping devices, typically diodes and/or transistors (411,412) connected to the corresponding power supply conductors (V DD , V SS ). The use of multiple resistors helps avoid failure due to "hot spots" produced by an ESD event.
Inventors
- 👤 Yehuda Smooha
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 09:18
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
90 words
1 . An integrated circuit comprising an output buffer having a pull-up transistor (11) and a n-channel pull-down transistor (12) coupled to a bondpad (17) adapted to being connected to an external conductor, CHARACTERIZED in that said integrated circuit further comprises an electrostatic discharge protection resistance means (14, 14′, 406 ... 408) having a resistance of greater than 1 ohm located in the path between the drain of said n-channel transistor (12) and said bondpad (17), and still further comprises voltage clamping means (15, 16) connected to said bondpad (17).
Claim 2
Dependent Claim
90 words
1 . An integrated circuit comprising an output buffer having a pull-up transistor (11) and a n-channel pull-down transistor (12) coupled to a bondpad (17) adapted to being connected to an external conductor, CHARACTERIZED in that said integrated circuit further comprises an electrostatic discharge protection resistance means (14, 14′, 406 ... 408) having a resistance of greater than 1 ohm located in the path between the drain of said n-channel transistor (12) and said bondpad (17), and still further comprises voltage clamping means (15, 16) connected to said bondpad (17).
Claim 3
Dependent Claim
64 words
2 . The integrated circuit of claim 1 wherein said integrated circuit comprises at least two levels of metal conductors, and wherein the drain of said pull-up transistor and the drain of said n-channel pull-down transistor are coupled to a common output node (13), and wherein said electrostatic discharge protection resistance means (14) is connected between said output node (13) and said bondpad (17).
Claim 4
Dependent Claim
54 words
3 . The integrated circuit of claim 1 wherein the drain of said pull-up transistor and the drain of said n-channel pull-down transistor are coupled to a common output node (13), and wherein said electrostatic discharge protection resistance means (14′) is connected between the drain of said n-channel pull-down transistor and said bondpad (17).
Claim 5
Dependent Claim
23 words
4 . The integrated circuit of claim 1 wherein said electrostatic discharge protection resistance means has a resistance of greater than 2 ohms.
Claim 6
Dependent Claim
23 words
5 . The integrated circuit of claim 1 wherein said electrostatic discharge protection resistance means has a resistance of less than 20 ohms.
Claim 7
Dependent Claim
31 words
6 . The integrated circuit of claim 1 wherein said output transistors have silicided gate, source, and drain electrodes, and said electrostatic discharge protection resistance means comprises a metal silicide conductor.
Claim 8
Dependent Claim
84 words
7 . The integrated circuit of claim 1 wherein said voltage clamping means is a pair of diodes, wherein the first diode (15) of said pair has a p-type anode region connected to said bondpad and an n-type cathode region connected to a positive power supply voltage conductor (V DD ), and the second diode (16) of said pair has a n-type cathode region connected to said bondpad and a p-type anode region connected to a negative power supply voltage conductor V SS ).
Claim 9
Dependent Claim
48 words
8 . The integrated circuit of claim 1 wherein said n-channel pull-down transistor (403 ... 405) comprises multiple drain regions, and still further CHARACTERIZED in that said electrostatic discharge protection resistance means comprises separate resistors (406 ... 408) that connect said multiple drain regions to said bondpad (410).
Claim 10
Dependent Claim
30 words
9 . The integrated circuit of claim 8 wherein said separate resistors are formed in a deposited conductor level overlying the semiconductor substrate in which said integrated circuit is formed.
Claim 11
Dependent Claim
28 words
10 . The integrated circuit of claim 9 wherein said deposited conductor level comprises a material selected from the group consisting of doped polysilicon and a metal silicide.
Claim 12
Dependent Claim
32 words
11 . The integrated circuit of claim 9 wherein said deposited conductor level is a metal silicide that is also formed on the gate, source, and drain electrodes of said pull-down device.
Claim 13
Dependent Claim
24 words
12 . The integrated circuit of claim 8 wherein each of said resistors has a resistance in the range of 1 to 100 ohms.
Claim 14
Dependent Claim
24 words
13 . The integrated circuit of claim 8 wherein each of said resistors has a resistance in the range of 5 to 50 ohms.
Claim 15
Dependent Claim
19 words
14 . The integrated circuit of claim 8 wherein said separate resistors physically contact said bondpad at its periphery.
Claim 16
Dependent Claim
23 words
The integrated circuit of claim 1 wherein said over-voltage clamping means includes a bipolar transistor (412) for clamping negative voltages on said bondpad.
Claim 17
Dependent Claim
43 words
The integrated circuit of claim 1 wherein said pull-up device is a p- channel field effect transistor formed in a n-tub region, wherein the junction formed by the p+ drain region and the n-tub region provides for clamping positive voltages on said bondpad.
Claim 18
Dependent Claim
16 words
The integrated circuit of claim 1 wherein said pull-up device is a p-channel field effect transistor.
Claim 19
Dependent Claim
18 words
18 . The integrated circuit of claim 1 wherein said pull-up device is an n-channel field effect transistor.
References Cited (Backward Citations)
EP0257774A1
Cited
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