TDMA satellite communications system operating in wide and narrow aperture modes for receiving bursts of various timing deviations

Claim 2

A satellite communications system having a central earth station and a plurality of terminal earth stations establishing a satellite channel with the central earth station via a geosynchronous satellite, the central earth station transmitting a time slot assignment signal and a reference timing signal to the terminal stations via the satellite channel to allow the terminal earth stations to send bursts on time slots specified by the assignment signal and establish a timing reference for timing said bursts, and including detector means for detecting said bursts from the terminal stations, a carrier and clock recovery circuit for recovering a carrier and clock pulses from the output of the detector means, and a unique word detector for detecting a unique word contained in the burst detected by the detector means, the central earth station comprising: timing means for generating a local timing signal synchronously with said reference timing signal; delay means for introducing a delay to the local timing signal by an amount corresponding to a minimum round-trip propagation delay of the satellite communications system; first control means responsive to said delayed local timing signal for controlling said carrier and clock recovery circuit to recover said carrier and clock pulses, generating a wide aperture gating pulse, and detecting an output signal from said unique word detector in the presence of said wide aperture gating pulse; and second control means responsive to said detected output signal for controlling said carrier and clock recovery circuit to recover said carrier and clock pulses, generating a narrow aperture gating pulse, and detecting an output signal from said unique word detector in the presence of the narrow aperture gating pulse.

Claim 3

A satellite communications systems as claimed in claim 1, wherein said first and second control means comprise: first counter means for incrementing a first binary count at clock intervals and resetting the count to an initial value of time-slot intervals, said first counter means being further resettable to said initial value in response to the delayed timing signal; first control signal generator means responsive to said first binary count for generating a first control signal for controlling said carrier and clock recovery circuit for recovering said carrier and clock pulses and for generating a wide aperture gating pulse; second counter means for incrementing a second binary count at clock intervals and resetting the second binary count to an initial value at said time-slot intervals, said second counter means being further resettable in response to a reset pulse applied thereto; second control signal generator means responsive to said second binary count for generating a second control signal for controlling said carrier and clock recovery circuit to recover said carrier and clock pulses and for generating a narrow aperture gating pulse; an aperture gate connected to the output of said unique word detector for passing an output signal from said unique word detector to said second counter means as said reset pulse in the presence of an aperture gating pulse applied thereto; selector means having a first position for coupling said first control signal to said carrier and clock recovery circuit and coupling said wide aperture gating pulse to said aperture gate and a second position for coupling said second control signal to said carrier and clock recovery circuit and coupling said narrow aperture gating pulse to said aperture gate; and control means for initially switching said selector means to said first position, switching the selector means to the second position in response to an output signal from said aperture gate, and switching the selector means back to said first position when no signal appears subsequently at the output of said gate.

Claim 4

A satellite communications system as claimed in claim 2, wherein said control means comprises: a flip-flop responsive to the output of said aperture gate for assuming a first binary state; and means for switching said flip-flop to a second binary state in response to either of said wide or narrow aperture gating pulse at the output of said selector means, said selector means being responsive to the binary states of of said flip-flop.

Claim 5

A satellite communications system as claimed in claim 3, wherein said switching means comprises a counter resettable in response to the output of said aperture gate for counting aperture gating pulses at the output of said selector means and resetting said flip-flop when the count of said gating pulses reaches a predetermined value.

Claim 6

A satellite communications system as claimed in claim 1, wherein said first and second control means comprise: first counter means for incrementing a first binary count at clock intervals and resetting the count to an initial value at time-slot intervals, said first counter means being further resettable to said initial value in response to the delayed timing signal; first control signal generator means responsive to said first binary count for generating a first control signal for controlling said carrier and clock recovery circuit to recover said carrier and clock pulses and for generating a wide aperture gating pulse; second counter means for incrementing a second binary count at clock intervals and resetting the second binary count to an initial value at said time-slot intervals, said second counter means being further resettable in response to a reset pulse applied thereto; second control signal generator means responsive to said second binary count for generating a second control signal for controlling said carrier and clock recovery circuit to recover said carrier and clock pulses and for generating a narrow aperture gating pulse; an aperture gate connected to the output of said unique word detector for gating an output signal from said unique word detector in the presence of an aperture gating pulse applied thereto; selector means having a first position for coupling said first control signal to said carrier and clock recovery circuit and coupling said wide aperture gating pulse to said aperture gate and a second position for coupling said second control signal to said carrier and clock recovery circuit and coupling said narrow aperture gating pulse to said aperture gate, said selector means initially assuming said first position; memory means having a plurality of storage locations for storing said second binary count into one of the locations in response to the output of said aperture gate; unique word counter means for counting an output signal of said aperture gate to produce a count representing the number of unique words that occur during a period defined either by said wide or narrow aperture gating pulse; comparator means for generating an equality pulse when said second binary count equals a reference value and applying the equality pulse to said second counter means as said reset pulse, said reference value being normally set at a maximum count value of said second counter means; and control means for deriving an average value of the second binary counts stored in the locations of said memory means when said unique word representative count reaches a predetermined value, setting said reference value to said average value, and causing said selector means to assume said second position when said equality pulse is generated by said comparator means.

Claim 7

A satellite communications system as claimed in claim 5, further comprising time slot counter means for counting the aperture gating pulses supplied to said aperture gate to produce a count representing the number of time slots, wherein said control means causes said selector means to assume said first position when said time slot representative count reaches a second predetermined value before said unique word representative count reaches the first-mentioned predetermined value, said second predetermined value being greater said first predetermined value.

Claim 8

A satellite communications system as claimed in claim 5, wherein said control means is programmed to perform the steps of: a) causing said selector means to assume said first position; b) clearing said memory means and resetting said unique word counter means to zero, and setting said reference value to a maximum binary count of said second counter means; c) detecting when said unique word representative count is equal to a predetermined value; d) deriving an average value of the second binary counts stored in the locations of said memory means; e) setting said reference value to said average value; f) detecting when said equality pulse is generated by said comparator means; and g) causing said selector means to assume said second position and repeating the steps (b) to (f).

Claim 9

A satellite communications system as claimed in claim 5, wherein said control means is programmed to perform the steps of: a) causing said selector means to assume said first position; b) clearing said memory means and resetting said unique word counter means and said time slot counter means to zero, and setting said reference value to a maximum binary count of said second counter means; c) detecting whether said unique word representative count is equal to a first predetermined value; d) if said unique word representative count is not equal to said first predetermined value, detecting whether said time slot representative count is equal to a second predetermined value greater than said first predetermined value; e) if said time slot representative count is not equal to said second predetermined value, repeating the step (d) and if said time slot representative count is equal to said second predetermined value, repeating the steps (a) to (d); f) if said unique word representative count is equal to said first predetermined value, deriving an average value of second binary counts stored in the locations of said memory means; g) setting said reference value to said average value; h) detecting when said equality pulse is generated by said comparator means; and i) causing said selector means to assume said second position and repeating the steps (b) to (h).