Digital signal reproducing apparatus

Claim 2

Apparatus for regenerating a coded digital signal, the apparatus comprising: input means (41 to 47) for supplying an input digital signal (Sc) representing said coded digital signal; interference cancellation equalising means (1 to 19; 21 to 30) connected to said input means (41 to 47) for cancelling an interference component from said input digital signal (Sc) and including compensating means (7;24) for high frequency compensating the input digital signal (Sc), extracting means (8 to 19; 25 to 30) for extracting lntercode interference (S2,S3) from the compensated digital signal (Sd), and subtracting means (5,6;23) for subtracting the extracted intercode interference from said input digital signal (Sc) to produce a waveform equalised signal (S4); and decoding means (38) connected to said interference cancellation equalising means (1 to 19; 21 to 30) for producing samples (S5) of said waveform equalised signal and correlating said samples to regenerate the coded digital signal.

Claim 3

Apparatus according to claim 1, wherein said input means comprises magnetic reproducing means (47,48) for reproducing said input digital signal (Sc) from a magnetic medium (46).

Claim 4

Apparatus according to claim 1 or claim 2, wherein said compensating means for high frequency compensating the input digital signal (Sc) comprises a linear equaliser (7;24) for emphasising high frequency components in said input digital signal (Sc).

Claim 5

Apparatus according to claim 1, claim 2 or claim 3, wherein said extracting means comprises comparator means (10,11;25) for receiving the high frequency compensated digital signal (Sd) and comparing it with a threshold level to produce a comparator output if the high frequency compensated digital signal (Sd) exceeds said threshold level, plural stage shift register means (12,16;27) for receiving and shifting therethrough the comparator output from said comparator means (10,11;25), and summing means (13 to 15, 17 to 19; 28 to 30) for summing the contents of selected stages of said shift register means (12,16;27).

Claim 6

Apparatus according to claim 4, comprising average level detecting means (26) for detecting an average level of said high frequency compensated digital signal (Sd) and supplying said average level to said comparator means (25) as said threshold level.

Claim 7

Apparatus according to claim 4, wherein the high frequency compensated digital signal (Sd) is formed of successive bit cells of pre-coded digital information, and said extracting means comprises encoding means (8,9) connected to said compensating means (7) for encoding the pre-coded digital information from said compensated digital signal (Sd) and supplying encoded bit cell information (Se) to said comparator means (10,11).

Claim 8

Apparatus according to claim 6, wherein said encoding means (8,9) exhibits a transfer characteristic [1+D], wherein D is a bit cell period.

Claim 9

Apparatus according to claim 6 or claim 7, wherein said encoding means comprises delay means (9) for delaying the high frequency compensated digital signal (Sd) by a bit cell period, and summing means (8) for summing the delayed and undelayed compensated digital signal.

Claim 10

Apparatus according to any one of claims 4 to 8, wherein said comparator means comprises positive and negative comparators (10, 11) for comparing said compensated digital signal (Se) with positive and negative threshold levels to produce respective comparator outputs if the compensated digital signal exceeds said positive or negative threshold levels, said plural stage shift register means comprises respective plural stage shift registers (12, 16) for receiving the comparator outputs from respective ones of the positive and negative comparators (10, 11), and said summing means comprises respective summing circuits (13 to 15, 17 to 19), each for summing the contents of selected stages of a respective shift register (12, 16) to produce respective summed outputs (S2, S3).

Claim 11

Apparatus according to claim 9, wherein said input digital signal is a pre-coded digital signal (Sc) reproduced from a magnetic medium (46), and said subtracting means comprises correcting means (1 to 4) for receiving said pre-coded digital signal (Sc) to correct bit interference caused by said magnetic medium (46) and to produce a corrected waveform (S1), and respective subtracters (5,6) connected in cascade to said correcting means (1 to 4), each for receiving a summed output (S2,S3) from a respective summing circuit (13 to 15, 17 to 19) to subtract the summed output (S2,S3) from said corrected waveform (S1) and thereby produce said waveform equalised signal (S4).

Claim 12

Apparatus according to claim 10, wherein each summing circuit includes weighting means (13,14; 17,18) for weighting the contents of the selected stages which are summed.

Claim 13

Apparatus according to claim 11, wherein said correcting means includes a low gain linear equaliser (4) for applying the corrected waveform (S1) to the cascaded subtracters (5, 6).

Claim 14

Apparatus according to claim 12, wherein said input digital signal (Sc) is formed of successive bit cells of pre-coded digital information, and said correcting means includes delay means (3) for delaying said input digital signal (Sc) by a bit cell period, and summing means (2) for summing the delayed and undelayed input digital signal and supplying the summed signal to said low gain linear equaliser (4).

Claim 15

Apparatus according to any one of claims 9 to 13, wherein each shift register (12,16) includes a predetermined stage and stages preceding and succeeding said predetermined stage, the contents of said preceding and succeeding stages being supplied to a respective summing circuit (15,19).

Claim 16

Apparatus according to claim 14, wherein said preceding and succeeding stages are adjacent said predetermined stage.

Claim 17

Apparatus for recovering a serial digital signal that has been recorded on a magnetic medium (46) in pre-coded form 1/[1-D²], wherein D is a bit interval of an original serial digital signal (Sa), said apparatus comprising: reproducing means (47,48) for reproducing the pre-coded digital signal from said magnetic medium (46); equalising means (7) connected to said reproducing means (47,48) for high frequency compensation equalising of the reproduced pre-coded digital signal (Sc); encoding means (8,9) for [1+D] encoding of the reproduced equalised digital signal (Sd) to produce a [1+D] encoded digital signal (Se); extraction means (10 to 19) connected to said encoding means (8,9) for extracting intercode interference components (S2, S3) from the encoded digital signal (Se); means (1 to 4) connected to said reproducing means (47,48) for reducing interbit interference in the reproduced pre-coded digital signal (Sc) to produce a corrected waveform signal (S1) representing the original digital signal; subtracting means (5,6) for subtracting the extracted intercode interference components (52,53) from the corrected waveform signal (S1) to produce a waveform equalised signal (S4); and correlation decoding means (38) connected to said subtracting means (5,6) for recovering the original digital signal as a function of the correlation of samples of said waveform equalised signal (S4).

Claim 18

Apparatus for recovering a serial digital signal that has been recorded on a magnetic medium (46) in pre-coded form 1/[1-D²], wherein D is a bit interval of an original serial digital signal (Sa), said apparatus comprising: reproducing means (47,48) for reproducing the pre-coded digital signal from said magnetic medium (46); equalising means (7) connected to said reproducing means (47,48) for high frequency compensation equalising of the reproduced pre-coded digital signal (Sc); encoding means (8,9) for [1+D] encoding of the reproduced equalised digital signal (Sd) to produce a [1+D] encoded digital signal (Se); extraction means (10 to 19) connected to said encoding means (8,9) for extracting intercode interference components (S2, S3) from the encoded digital signal (Se); means (1 to 4) connected to said reproducing means (47,48) for reducing interbit interference in the reproduced pre-coded digital signal (Sc) to produce a corrected waveform signal (S1) representing the original digital signal; subtracting means (5,6) for subtracting the extracted intercode interference components (52,53) from the corrected waveform signal (S1) to produce a waveform equalised signal (S4); and correlation decoding means (38) connected to said subtracting means (5,6) for recovering the original digital signal as a function of the correlation of samples of said waveform equalised signal (S4).

Claim 19

Apparatus according to claim 16, wherein said means for reducing interbit interference in the reproduced pre-coded digital signal (Sc) includes additional encoding means (2 to 4) for [1+D] encoding of the reproduced digital signal (Sc).

Claim 20

Apparatus according to claim 17, wherein said additional encoding means includes low gain equalising means (4) for providing low gain high frequency compensation to the [1+D] encoded reproduced digital signal.

Claim 21

Apparatus according to claim 16, claim 17 or claim 18, wherein said extraction means comprises bit selecting means (12,16) for selecting bits that precede and succeed, respectively, a predetermined bit in said encoded digital signal (Se), weighting means (13,14; 17,18) for weighting the selected bits, and summing means (15,19) for summing the weighted bits to produce said intercode interference components (S2,S3).

Claim 22

Apparatus according to claim 16, claim 17 or claim 18, wherein said extraction means comprises first and second comparator means (10,11) for sensing when the encoded digital signal (Se) exceeds positive and negative threshold levels, respectively, to produce bit indications thereof, first and second plural stage shift register means (12,16) for receiving and shifting therethrough the bit indications produced by said first and second comparator means (10,11), respectively, first and second weighting means (13,14; 17,18) connected to selected stages of said first and second shift register means (12,16), respectively, to weight the bit indications in said selected stages, and first and second summing means (15,19), each for summing the weighted bit indications of the selected stages of a respective shift register means (12,16) to produce an intercode interference component (S2,S3).

Claim 23

Apparatus according to claim 20, wherein said subtracting means comprises first and second subtracters (5,6) for subtracting first and second intercode interference components (S2,S3) produced by said first and second summing means (15,19) from said corrected waveform signal (S1).

Claim 24

Apparatus according to claim 21, wherein said first and second subtracters (5,6) are connected in cascade.

Claim 25

Apparatus according to claim 20, claim 21 or claim 22, wherein said selected stages of said first and second shift register means (12,16) comprise a stage preceding a predetermined stage and a stage succeeding said predetermined stage in each respective shift register means (12,16).

Claim 26

Apparatus for recovering a serial digital signal from an electromagnetic conversion system (41 to 48) having a transfer characteristic [1-D], wherein D is a bit interval of an original digital signal (Sa) supplied to said electromagnetic conversion system (41 to 48) in pre-coded form 1/[1-D²], said apparatus comprising wave shape correcting means (1 to 4) for correcting the wave shape of a serial digital signal (Sc) received from said electromagnetic conversion system (41 to 48), extracting means (7 to 19) for extracting from the digital signal (Sc) received from said electromagnetic conversion system (41 to 48) a high frequency compensated intercode interference component (S2,S3), subtracting means (5,6) for subtracting the extracted intercode interference component (S2,S3) from the wave shape corrected digital signal (S1) received from said electromagnetic conversion system (41 to 48) to produce a waveform equalised signal (S4), and decoding means (38) for decoding said waveform equalised signal (S4) to recover original digital information (S5).

Claim 27

Apparatus for recovering a serial digital signal from an electromagnetic conversion system (41 to 48) having a transfer characteristic [1-D], wherein D is a bit interval of an original digital signal (Sa) supplied to said electromagnetic conversion system (41 to 48) in pre-coded form 1/[1-D²], said apparatus comprising wave shape correcting means (1 to 4) for correcting the wave shape of a serial digital signal (Sc) received from said electromagnetic conversion system (41 to 48), extracting means (7 to 19) for extracting from the digital signal (Sc) received from said electromagnetic conversion system (41 to 48) a high frequency compensated intercode interference component (S2,S3), subtracting means (5,6) for subtracting the extracted intercode interference component (S2,S3) from the wave shape corrected digital signal (S1) received from said electromagnetic conversion system (41 to 48) to produce a waveform equalised signal (S4), and decoding means (38) for decoding said waveform equalised signal (S4) to recover original digital information (S5).

Claim 28

Apparatus according to claim 24, wherein said extracting means comprises a linear equaliser (7) for emphasising the high frequency characteristics of the digital signal (Sc) received from said electromagnetic conversion system (41 to 48), level detecting means (10,11) for detecting when the high frequency emphasised digital signal (Se) exceeds a threshold level to produce successive bit indications, bit selecting means (12,16) connected to said level detecting means (10,11) for selecting particular ones of said successive bit indications, weighting means (13,14; 17,18) for weighting the selected bit indications, and summing means (15,19) for summing the weighted bit indications to produce a high frequency compensated intercode interference component (S2,S3).

Claim 29

Apparatus according to claim 25, wherein said level detecting means includes a comparator (25), and average level generating means (26) for generating an average level of the high frequency emphasised digital signal and supplying the generated average level to said comparator (25) as said threshold level.

Claim 30

Apparatus according to claim 25, wherein said level detecting means comprises [1+D] encoding means (8,9) connected to said linear equaliser (7) for producing a [1+D] encoded, high frequency emphasised digital signal (Se), and first and second comparators (10,11) having first and second threshold levels for detecting when the [1+D] encoded, high frequency emphasised digital signal (Se) is greater than said first threshold level and is less than said second threshold level to produce respective first and second sets of successive bit indications.

Claim 31

Apparatus according to claim 27, wherein said bit selecting means comprises first and second plural stage shift registers (12,16) for receiving and shifting therethrough said respective first and second sets of successive bit indications, each shift register (12,16) having selected stages connected to said weighting means (13,l4; 17,18) to supply thereto bit indications which precede and succeed, respectively, a predetermined bit indication.

Claim 32

Apparatus according to claim 28, wherein said weighting means comprises first and second weighting circuits (13,14; 17,18), each connected to a respective one of said shift registers (12,16) to receive said preceding and succeeding bit indications therefrom.

Claim 33

Apparatus according to any one of claims 25 to 29, wherein said subtracting means comprises first and second subtracters (5,6) connected in cascade to said wave shape correcting means (1 to 4) and supplied with outputs (S2,S3) from said summing means (15,19) to subtract said outputs from the wave shape corrected digital signal (S1).

Claim 34

Apparatus according to any one of claims 24 to 30, wherein said wave shape correcting means comprises [1+D] encoding means (2,3) for producing a [1+D] encoded digital signal, and low gain equalising means (4) for providing low gain high frequency compensation to said [1+D] encoded digital signal.