EP0369264A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Multiprocessor system having distributed shared resources and deadlock prevention
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1989-11-04
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Granted: —
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Expires: 2009-11-04
Abstract
Abstract In a data processing multiprocessor system having distributed shared resources where each system processor (7) is provided with at least a local memory (8) to which it get access through a local bus (11), and with an interface unit (10) for connection of the local bus (11) to a system bus (5) and wherein each of the system processors may have access the local memory of another processor through its own local bus, its own interface unit, the system bus and the local bus of the other processor, deadlock is prevented by providing a bypass unit (40) of the interface unit (10) for enabling access from the system bus to the local bus through the bypass unit, a block (9) connected between the local bus and the interface unit (10) for latching system bus access requests received from an agent processor on the local bus, and a block (12) for isolation of the agent processor outputs from local bus, so that each agent processor may post read/write operations in the related latching block(9) for latching bus access requests and thereafter release its own local bus without waiting completion of the operation, whereby the local bus is available to receive access requests received from the system bus through the bypass unit (40), the operation pending in the latching block (9) being completed, if a read operation, by reconnection of the agent processor (7) and the latching block (9) to the local bus.
Inventors
- 👤 Carlo Bagnoli
- 👤 Guido Perrella
- 👤 Tommaso Majo
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 21:30
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/161; G06F13/00; G06F13/14; G06F13/36; G06F13/362; G06F13/364; G06F15/163; G06F15/167
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
205 words
1) Data processing multiprocessor system having distributed shared resources where each processing unit (CPU) comprises a processor (7), a local memory (8) a system bus interface unit (10) a local bus (11) for communication among said processor (7) said local memory (8) and said interface unit(10) and an arbitration unit (13) for arbitrating access to said local bus, characterized in that each CPU comprises: - an isolation block (12) of said processor (7) from said local bus, - an isolation and latching block (9 SBOUT) interposed between said local bus and said interface unit (10) for "posting" access commands to said system bus, said access commands being generated by said processor, - an input block (40-SBIN) in parallel to said interface unit for receiving from said system bus and latching access requests to said local memory (8), - said isolation and latching block (9) comprising first circuit means for generating request signal for reconnection to said local bus on receipt of data from said system bus, - said isolation block (12) comprising second circuit means for reconnecting said processor to said local bus, as a receiver, when said isolation and latching block (9) is reconnected to said local bus on authorization by said arbitration unit.
Claim 2
Dependent Claim
205 words
1) Data processing multiprocessor system having distributed shared resources where each processing unit (CPU) comprises a processor (7), a local memory (8) a system bus interface unit (10) a local bus (11) for communication among said processor (7) said local memory (8) and said interface unit(10) and an arbitration unit (13) for arbitrating access to said local bus, characterized in that each CPU comprises: - an isolation block (12) of said processor (7) from said local bus, - an isolation and latching block (9 SBOUT) interposed between said local bus and said interface unit (10) for "posting" access commands to said system bus, said access commands being generated by said processor, - an input block (40-SBIN) in parallel to said interface unit for receiving from said system bus and latching access requests to said local memory (8), - said isolation and latching block (9) comprising first circuit means for generating request signal for reconnection to said local bus on receipt of data from said system bus, - said isolation block (12) comprising second circuit means for reconnecting said processor to said local bus, as a receiver, when said isolation and latching block (9) is reconnected to said local bus on authorization by said arbitration unit.
Claim 3
Dependent Claim
107 words
2) System as claimed in claim 1, wherein at least one CPU of said system comprises a local memory input block (8A) for latching access requests to said local memory and for isolating said local memory from said local bus, said local memory input block (8A) comprising third circuit means for generating a request signal for reconnection to said local bus when data read out from said local memory becomes available, and wherein said input block (40) comprises fourth circuit means for reconnecting to said local bus as a data receiver, when said local memory is reconnected to said local bus on authorization by said arbitration unit.
Claim 4
Dependent Claim
58 words
3) System as claimed in claim 2, wherein said isolation block (12) and said input block (40) comprise fifth and sixts circuit means respectively for identification of said blocks as destination units on reconnection to said local bus of either said isolation and latching block (9) or said local memory input block (8A) authorized by said arbitration unit.
Claim 5
Dependent Claim
92 words
4) System as claimed in claim 3 wherein said arbitration unit receives local bus access request signals from a plurality of requesting units or "masters" together with an indication of a destination unit for said access requests and comprises means 34,35,36,37,38) for receiving at least a signal (LMBSY, LMRPG) indicative of the availability of a destination unit to receive an access request and for generating a local bus access authorization (ENSB) based on the priority assigned to the requesting units and the availability of a destination unit to receive said access request.
Claim 6
Dependent Claim
161 words
5) Data processing system in which a plurality of requesting units or "masters" compete for access to a common communication bus, through which they can select one among a plurality of receiving units or "slaves" for directing said selected unit to perform predetermined operations, by means of a communication bus access request for operation sent to an arbitration unit, said arbitration unit granting access to the more prioritary master among the competing ones, characterized by that said arbitration unit comprises first means for receiving signals from said slaves indicative of the availability of said slaves to perform said predetermined operation directed by said bus access requests, second means for receiving from said masters an indication of the selected destination slave and circuit means for granting access to said common communication bus on the basis of a priority level assigned to each of said masters and the availability of the destination slave selected to receive said communication bus access request for operation.
Claim 7
Dependent Claim
161 words
5) Data processing system in which a plurality of requesting units or "masters" compete for access to a common communication bus, through which they can select one among a plurality of receiving units or "slaves" for directing said selected unit to perform predetermined operations, by means of a communication bus access request for operation sent to an arbitration unit, said arbitration unit granting access to the more prioritary master among the competing ones, characterized by that said arbitration unit comprises first means for receiving signals from said slaves indicative of the availability of said slaves to perform said predetermined operation directed by said bus access requests, second means for receiving from said masters an indication of the selected destination slave and circuit means for granting access to said common communication bus on the basis of a priority level assigned to each of said masters and the availability of the destination slave selected to receive said communication bus access request for operation.
References Cited (Backward Citations)
No citation records indexed.
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