Process for forming trench isolation structures in a silicon substrate for CMOS and NMOS devices

Abstract

Abstract Formation of a P+ channel-stop diffused region adjacent to substantially vertical lateral walls of trenches etched in the silicon for forming BOX isolation structures in CMOS and NMOS devices is achieved by growing a thermal oxide barrier layer on the silicon walls within the trench, depositing a BSG dopant source layer by CVD techniques, thermally diffusing dopant atoms from the source layer through the thermal oxide barrier layer into the silicon substrate for producing the desired diffused region adjacent to the trench's walls. The dopant source layer and the thermal oxide barrier layer are removed thereafter and the fabrication process may proceed in an usual way.

Inventors

• 👤 Orio Bellezza

Bibliographic Details