Heretojunction bipolar transistor

Claim 2

In a bipolar transistor of the type having in a compound semiconductor body an exposed surface base layer over a buried layer forming a p-n junction therewith and with a smaller area epitaxial electrode forming a p-n junction with said base layer at said exposed surface, said epitaxial electrode extending a distance vertically with respect to said exposed surface, the intermediate manufacturing product comprising: said epitaxial electrode having an overhanging por­tion at the portion thereof separated from said exposed surface, said overhanging portion extending a specific lateral distance beyond the ateral extent of said electrode at contact with said exposed layer, and said base layer having a high conductivity portion, said high conductivity portion surrounding the area of contact of said epitaxial electrode with said base layer and terminating proximate to said epitaxial electrode by at most said specific dis­tance.

Claim 3

The improvement of claim 1 wherein said epitaxial electrode is the collector electrode of said transis­tor and said buried layer is the emitter electrode of said transistor.

Claim 4

The improvement of claim 1 wherein said epitaxial electrode is the emitter electrode of said transistor and said buried layer is the collector electrode of said transistor.

Claim 5

The intermediate manufacturing product of claim 3 wherein said overhanging portion results from said emitter electrode having a trapezoidal shape with the smaller parallel side thereof in contact with said base layer.

Claim 6

The intermediate manufacturing product of claim 3 wherein said overhanging portion is a deposited material on the vertical sides of said emitter electrode.

Claim 7

The intermediate manufacturing product of claim 3 wherein said overhanging portion results from a separate layer positioned on and extending beyond the vertical sides of a two-epitaxial layer body of said emitter electrode.

Claim 8

A heterojunction bipolar transistor comprising in combination, a compound semiconductor monocrystalline body, said body having a larger area base electrode layer forming a p-n junction with a buried electrode ayer and a smaller area epitaxial electrode forming a p-n junction with said base electrode layer on the other side thereof, said base electrode layer having an extrinsic portion of high conductivity surrounding and extend­ing proximate to but separated from by a specific dimension, said smaller area electrode p-n junction periphery thereby defining an intrinsic base elec­trode area and a base electrode to buried electrode p-n junction area, a metal contact to said extrinsic portion of said base layer terminating at said specific dimension from said smaller area electrode, an isolation member in said body extending at least through said buried layer, an insulation layer surrounding said smaller area electrode, conformally covering said metal contact and having a planar surface flush with said small area electrode, and contact members positioned on said planar surface and providing a separate electrical connection to each of said small electrode, said metal contact and said buried electrode.

Claim 9

A heterojunction bipolar transistor comprising in combination, a compound semiconductor monocrystalline body, said body having a larger area base electrode layer forming a p-n junction with a buried electrode ayer and a smaller area epitaxial electrode forming a p-n junction with said base electrode layer on the other side thereof, said base electrode layer having an extrinsic portion of high conductivity surrounding and extend­ing proximate to but separated from by a specific dimension, said smaller area electrode p-n junction periphery thereby defining an intrinsic base elec­trode area and a base electrode to buried electrode p-n junction area, a metal contact to said extrinsic portion of said base layer terminating at said specific dimension from said smaller area electrode, an isolation member in said body extending at least through said buried layer, an insulation layer surrounding said smaller area electrode, conformally covering said metal contact and having a planar surface flush with said small area electrode, and contact members positioned on said planar surface and providing a separate electrical connection to each of said small electrode, said metal contact and said buried electrode.

Claim 10

The transistor of claim 7 wherein said smaller area electrode is the emitter.

Claim 11

The transistor of claim 8 wherein said emitter is a trapezoid in shape.

Claim 12

The transistor of claim 8 wherein said base electrode layer is of P-AlGaAs, said buried layer is n-AlGaAs and said emitter is made up of a first in n-AlGaAs layer adjacent said base layer and a second n+GaAs layer remote from said base layer.

Claim 13

In a process of forming a bipolar transistor in a compound semiconductor body wherein a larger area base electrode layer forms on one side thereof a p-n junction with a buried electrode layer and on the other side of said base layer a smaller area electrode forms a p-n junction therewith, the improvement comprising the step of providing an overhang capability on the portion of said smaller area electrode separated from said p-n junction, said overhang imparting the combined properties of masking of said base layer in at least one of a conductivity conversion and a metal deposition peration orthogonally directed with respect to said base layer, ledge type direction change in shape in lift-off separation of deposited materials, and vertical distance processing guidance in an erosion operation conducted orthogonally with respect to said base layer.

Claim 14

In a process of forming a bipolar transistor in a compound semiconductor body wherein a larger area base electrode layer forms on one side thereof a p-n junction with a buried electrode layer and on the other side of said base layer a smaller area electrode forms a p-n junction therewith, the improvement comprising the step of providing an overhang capability on the portion of said smaller area electrode separated from said p-n junction, said overhang imparting the combined properties of masking of said base layer in at least one of a conductivity conversion and a metal deposition peration orthogonally directed with respect to said base layer, ledge type direction change in shape in lift-off separation of deposited materials, and vertical distance processing guidance in an erosion operation conducted orthogonally with respect to said base layer.

Claim 15

The process improvement of claim 11 wherein said conductivity conversion is through ion implantation.

Claim 16

The process improvement of claim 11 wherein said overhang is produced by a trapezoidal shape of said smaller area electrode.

Claim 17

The process improvement of claim 11 wherein said overhang is deposited layer extending beyond the sides of said smaller area electrode.

Claim 18

The process of forming a heterojunction bipolar transistor in a monocrystalline compound semiconduc­ tor body of a type wherein a larger area base elec­trode layer forms on one side thereof a p-n junction with a buried electrode layer and the other side thereof forms a p-n junction with a smaller area electrode comprising in combination the steps of: providing a multilayer monocrystalline body having at least said base layer in p-n junction relationship on said buried electrode layer, forming said smaller area electrode in p-n junction relationship on said base electrode layer, said forming step including the providing of an overhang member on the portion of said small area lectrode separated vertically from said base layer, said overhang member extending laterally beyond said small area electrode p-n junction a specific dis­tance, converting the conductivity of said base layer surrounding said small area electrode to high conductivity, said overhang serving as a mask in said conversion to delineate the edge location of said converted base layer region at a location proximate to but separated from said small area electrode p-n junction by said specific distance, depositing a metal on said converted portion of said base layer and on said small area electrode, separating the portions of said metal on said converted portion of said base layer and on said small area electrode, applying an insulating layer surrounding said small area electrode, applying a conformal planarizing material layer over said insulating layer, eroding the combination of said planarizing material layer and said insulating layer until there is a planar surface of insulating material that is flush with the higher portion of said small area electrode, and applying a separate metal contact on said planar surface for each of said small area electrode, said metal on said converted portion of said base and said buried electrode with electrical connections to each electrode.

Claim 19

The process of forming a heterojunction bipolar transistor in a monocrystalline compound semiconduc­ tor body of a type wherein a larger area base elec­trode layer forms on one side thereof a p-n junction with a buried electrode layer and the other side thereof forms a p-n junction with a smaller area electrode comprising in combination the steps of: providing a multilayer monocrystalline body having at least said base layer in p-n junction relationship on said buried electrode layer, forming said smaller area electrode in p-n junction relationship on said base electrode layer, said forming step including the providing of an overhang member on the portion of said small area lectrode separated vertically from said base layer, said overhang member extending laterally beyond said small area electrode p-n junction a specific dis­tance, converting the conductivity of said base layer surrounding said small area electrode to high conductivity, said overhang serving as a mask in said conversion to delineate the edge location of said converted base layer region at a location proximate to but separated from said small area electrode p-n junction by said specific distance, depositing a metal on said converted portion of said base layer and on said small area electrode, separating the portions of said metal on said converted portion of said base layer and on said small area electrode, applying an insulating layer surrounding said small area electrode, applying a conformal planarizing material layer over said insulating layer, eroding the combination of said planarizing material layer and said insulating layer until there is a planar surface of insulating material that is flush with the higher portion of said small area electrode, and applying a separate metal contact on said planar surface for each of said small area electrode, said metal on said converted portion of said base and said buried electrode with electrical connections to each electrode.

Claim 20

The process of claim 16 wherein said smaller area electrode is the emitter of said transistor having first and second epitaxial grown layers of semicon­ductor material.

Claim 21

The process of claim 17 wherein said first and second emitter layers are grown through an opening in a mask in contact with said base layer.

Claim 22

The process of claim 18 wherein said opening in said mask is provided with sloping sides having the larger opening on the side of said mask not in con­tact with said base layer providing thereby a trape­zoidal shape.

Claim 23

The process of claim 18 wherein said overhang is provided by depositing material on the uppermost portion of the sides of said emitter electrode.

Claim 24

The process of claim 17 wherein said emitter is formed by adding said first and second emitter layers in said multilayer monocrystalline body and eroding away all but said smaller area.

Claim 25

The process of claim 21 wherein said overhang is formed by depositing an overhanging layer on said emitter.

Claim 26

The process of forming a heterojunction bipolar transistor comprising in combination the steps of: providing a substrate having at least a p type GaAs base layer over an n type AlGaAs collector, forming an inverted trapezoid-shaped emitter on a portion of said base layer, said emitter being composed of a lower tub-shaped structure of n type AlGaAs contacting said base layer and n+ GaAs filling structure, forming extrinsic base by doping said base layer using said emitter as a mask, forming an ohmic contact to said extrinsic base by depositing a conductive material using said emitter as a mask, forming a planar insulator layer coplanar with the upper surface of said emitter and applying an ohmic wiring connection on said planar insulator layer for each of said emitter, said extrinsic base and said collector with contact to the specific electrode.

Claim 27

The process of forming a heterojunction bipolar transistor comprising in combination the steps of: providing a substrate having at least a p type GaAs base layer over an n type AlGaAs collector, forming an inverted trapezoid-shaped emitter on a portion of said base layer, said emitter being composed of a lower tub-shaped structure of n type AlGaAs contacting said base layer and n+ GaAs filling structure, forming extrinsic base by doping said base layer using said emitter as a mask, forming an ohmic contact to said extrinsic base by depositing a conductive material using said emitter as a mask, forming a planar insulator layer coplanar with the upper surface of said emitter and applying an ohmic wiring connection on said planar insulator layer for each of said emitter, said extrinsic base and said collector with contact to the specific electrode.

Claim 28

The process of forming a heterojunction bipolar transistor comprising in combination the steps of: providing a GaAs substrate having thereon successive layers of at least n+ GaAs, n AlGaAs, p GaAs, n AlGaAs, n+ GaAs and a first insulator, patterning said first insulator and n+ GaAs layers into a micron sized island member, reducing the area of said n+ GaAs layer of said island member by side etching thereof leaving an overhanging portion of said first insulator layer, ion implanting a p+ dopant into said n AlGaAs and p GaAs layers using said first insulator layer as a mask to form the high conductivity extrinsic base of said transistor, establishing an ohmic metal contact to said extrinsic base by depositing said metal using said first insu­lator as a mask, forming a second insulator layer over the resulting structure, planarizing to obtain a surface coplanar with the upper surface of said n+ GaAs in said island member, and providing an electrical contacting member on said planarizing surface connected to each of said n+ GaAs in said island, said extrinsic base and said n AlGaAs under said base.

Claim 29

The process of forming a heterojunction bipolar transistor comprising in combination the steps of: providing a GaAs substrate having thereon successive layers of at least n+ GaAs, n AlGaAs, p GaAs, n AlGaAs, n+ GaAs and a first insulator, patterning said first insulator and n+ GaAs layers into a micron sized island member, reducing the area of said n+ GaAs layer of said island member by side etching thereof leaving an overhanging portion of said first insulator layer, ion implanting a p+ dopant into said n AlGaAs and p GaAs layers using said first insulator layer as a mask to form the high conductivity extrinsic base of said transistor, establishing an ohmic metal contact to said extrinsic base by depositing said metal using said first insu­lator as a mask, forming a second insulator layer over the resulting structure, planarizing to obtain a surface coplanar with the upper surface of said n+ GaAs in said island member, and providing an electrical contacting member on said planarizing surface connected to each of said n+ GaAs in said island, said extrinsic base and said n AlGaAs under said base.

Claim 30

The process of forming a heterojunction bipolar transistor comprising in combination the steps of: providing a GaAs substrate having at least a p GaAs base layer over a n AlGaAs collector layer, said base layer being masked by a first insulator, said insulator having an opening therein, forming an emitter composed of a first layer of n GaAlAs and a second layer of n+ GaAs thereabove in said opening, with said second layer projecting above said first insulator, establishing a sidewall overhang member on said projecting second emitter layer, forming an extrinsic base in said p GaAs employing said overhand member as a mask to delineate the edge location thereof adjacent said emitter, providing a deposited metal on said extrinsic base and on said n⁺ GaAs second layer of said emitter, separating said deposited metal on said extrinsic base from said metal on said emitter by lift-off, forming a second insulator layer on the resulting structure, planarizing to obtain a planar surface composed of said second insulator and said emitter, and applying an electrical contacting member on said planarized surface connected to each of said emitter, said extrinsic base and said collector.

Claim 31

The process of forming a heterojunction bipolar transistor comprising in combination the steps of: providing a GaAs substrate having at least a p GaAs base layer over a n AlGaAs collector layer, said base layer being masked by a first insulator, said insulator having an opening therein, forming an emitter composed of a first layer of n GaAlAs and a second layer of n+ GaAs thereabove in said opening, with said second layer projecting above said first insulator, establishing a sidewall overhang member on said projecting second emitter layer, forming an extrinsic base in said p GaAs employing said overhand member as a mask to delineate the edge location thereof adjacent said emitter, providing a deposited metal on said extrinsic base and on said n⁺ GaAs second layer of said emitter, separating said deposited metal on said extrinsic base from said metal on said emitter by lift-off, forming a second insulator layer on the resulting structure, planarizing to obtain a planar surface composed of said second insulator and said emitter, and applying an electrical contacting member on said planarized surface connected to each of said emitter, said extrinsic base and said collector.