EP0367183A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
System for high speed computer graphics computation
Assignee: Philips GmbH
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Filing: 1989-10-30
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Granted: —
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Expires: 2009-10-30
Abstract
Abstract A high performance computer graphics image computation system architecture is disclosed. The system architecture includes a computational processor ring which includes a plurality of closely coupled computational subsystems. The computational subsystems operate asynchronously and each is interconnected with two adjacent computational subsystems. The architecture of the processor ring allows rapid communication between the computational subsystems while avoiding a deadlock condition. The system architecture also includes a video processor ring wherein a plurality of video processors are synchronously linked together. A plurality of local communication paths couple the computational subsystems to the video processors. The video processor ring is able to move massive amounts of data, in the form of digital video signals, from various points within the system. The computational processor ring is able to rapidly carry out graphic image computation tasks and graphic image data is moved around in the system by way of the video processor ring. The embodiments of the present invention allow the components of the computational processor ring and the video processor ring to be variably configured as one or more logical machines, each logical machine being assigned a particular graphic image computation task. The described embodiments are also readily expandable so that components may be added to the computational processor ring, the video processor ring, or at other locations in the system.
Inventors
- 👤 Leland K. Putnam
- 👤 Philip H. Lucht
- 👤 David K. Blair
- 👤 Scott K. Pritchett
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 21:19
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8007; G06F15/8015; G06T; G06T1/00; G06T1/20
Claims Analysis
Total Claims: 60
Claim 1
Independent Claim
261 words
A digital computing system adapted to carry out a plurality of processes which are necessary to rapidly compute graphic images, the system comprising: a plurality of computational subsystems, each computational subsystem having a parallel ring input and a parallel ring output, the ring output of each computational subsystem being connected to the ring input of one other computational subsystem such that a first communication ring is formed allowing high-speed communication between the computational subsystems; a plurality of digital video processors, each digital video processor having an input and an output, the output of each digital video processor being connected to the input of one other digital video processor such that a second communication ring is formed between the digital video processors; means for inputting and outputting information between an external computer and the first communication ring such that data may be exchanged between the external computer and the computational subsystems; means for exchanging information between a video device and the second communication ring such that video images may be exchanged between the digital video processors and the video device; and at least one local communication pathway, each local communication pathway connecting at least one computational subsystem to at least one digital video processor such that data may be rapidly transferred between the computational subsystems forming the first communication ring and the digital video processors forming the second communication ring and such that any number of computational subsystems and digital video processors may be grouped together to accomplish a graphic image processing task and output the completed image to a video device.
Claim 2
Dependent Claim
261 words
A digital computing system adapted to carry out a plurality of processes which are necessary to rapidly compute graphic images, the system comprising: a plurality of computational subsystems, each computational subsystem having a parallel ring input and a parallel ring output, the ring output of each computational subsystem being connected to the ring input of one other computational subsystem such that a first communication ring is formed allowing high-speed communication between the computational subsystems; a plurality of digital video processors, each digital video processor having an input and an output, the output of each digital video processor being connected to the input of one other digital video processor such that a second communication ring is formed between the digital video processors; means for inputting and outputting information between an external computer and the first communication ring such that data may be exchanged between the external computer and the computational subsystems; means for exchanging information between a video device and the second communication ring such that video images may be exchanged between the digital video processors and the video device; and at least one local communication pathway, each local communication pathway connecting at least one computational subsystem to at least one digital video processor such that data may be rapidly transferred between the computational subsystems forming the first communication ring and the digital video processors forming the second communication ring and such that any number of computational subsystems and digital video processors may be grouped together to accomplish a graphic image processing task and output the completed image to a video device.
Claim 3
Dependent Claim
269 words
A digital computing system as defined in claim 1 wherein the first communication ring is adapted for distributing data packets and wherein the first communication ring comprises a plurality of processors each containing one such interface, said processors being connected one to another to form a ring wherein packets of data may be transferred around the ring from one processor to another, said interface comprising: input storage means for temporary storage of said data packets as they are input to one processor from another processor of said ring; output buffer means for temporary storage of said data packets as they are transferred from one processor of said ring to the next, said output buffer having a storage capacity sized so as to limit the size of a data packet output therefrom such that no data packet can be output onto said ring where the output data packet is larger than the amount of storage capacity of any available input storage means of the processors on said ring; input control means, connected to said input storage means, for identifying whether data packet is addressed to the processor receiving the data packet at its input storage means, and if so, thereafter transferring the data packet to the addressed processor and permitting asynchronous processing of the data packet relative to other processors in the ring, and if not, preparing the data packet for transfer to the next processor in the ring; and output control means, connected to said output buffer means, for synchronously transferring data packets from the output buffer means of one processor to the input storage means of the next.
Claim 4
Dependent Claim
68 words
An interface as defined in claim 1 further comprising means for monitoring each data packet output onto said ring, so that if a data packet returns to the processor from which it was sent more than a predetermined number of times without having been received by another processor on the ring to which said data packet was sent, then said data packet may be removed from the ring.
Claim 5
Dependent Claim
130 words
An interface as defined in claim 3 further comprising means for communicating from said input storage means a status signal to the output buffer means from which a data packet is being sent to said input storage means, said status signal indicating when the input storage means is filled with data to a predetermined amount of its storage capacity, and wherein each said output control means comprises means for receiving a status signal from an input storage means so that as one processor transfers a data packet to the next processor in the ring, if available storage capacity of the input storage means of said next processor is less than said predetermined amount and further data input to said next processor would be temporarily halted by said output control means.
Claim 6
Dependent Claim
19 words
An interface as defined in claim 2 wherein said input storage means comprises a first-in first-out (FIFO) memory device.
Claim 7
Dependent Claim
81 words
An interface as defined in claim 2 wherein said output control means comprises an output arbitration state machine and wherein said output control means further comprises an output word counter connected to said output arbitration state machine and further comprising a first latch connected to the output of said output word counter, a second latch connected to said output buffer means on an input side thereof, and a third latch connected to said output buffer means on a output side thereof.
Claim 8
Dependent Claim
78 words
An interface as defined in claim 2 wherein said input control means comprises an input arbitration state machine and wherein said input control means further comprises an input word counter connected on an output side of said input storage means and connected on an input side of said input arbitration state machine, and an input buffer connected on said output side of said input storage means and connected on said input side of said input arbitration state machine.
Claim 9
Dependent Claim
23 words
A digital computing system as defined in claim 1 wherein the means for inputting and outputting information comprises a first communication ring controller.
Claim 10
Dependent Claim
37 words
A digital computing system as defined in claim 1 wherein the means for inputting and outputting comprises means for receiving a digital time code and means for generating and receiving machine control signals to control peripheral devices.
Claim 11
Dependent Claim
36 words
A digital computing system as defined in claim 9 wherein the means for inputting and outputting information further comprises means for receiving information from an external computer by both a serial bus and a communication network.
Claim 12
Dependent Claim
44 words
A digital computing system as defined in claim 1 wherein the means for exchanging information between a video device and the second communication ring comprises means for generating commands and addressing those commands to other digital video processors located on the second communication ring.
Claim 13
Dependent Claim
46 words
A digital computing system as defined in claim 11 wherein the means for exchanging information comprises means for placing information from a first peripheral video device onto the second communication ring and for passing information from the second communication ring to a second, peripheral video device.
Claim 14
Dependent Claim
43 words
A digital computing system as defined in claim 1 further comprising a local bus interconnecting the means for inputting and outputting with the means for exchanging information such that data may be passed between the first communication ring and the second communication ring.
Claim 15
Dependent Claim
178 words
A computing system capable of efficiently carrying out a plurality of processes necessary to generate computer graphic images, the system comprising: a plurality of computational subsystems, each computational subsystem adapted to carry out a computer graphics computation task, each computational subsystem including an input and an output; a first digital communication ring, the first communication ring connected the input and output of all the computational subsystems and providing communication among the computational subsystems; a plurality of video processors, each video processor capable of storing at least a portion of a video image frame; a second digital communication ring, the second communication ring connected to all of the video processors and providing communication among the video processors; means for interfacing an external computer with the first communication ring; means for interfacing a video image peripheral device with the second communication ring; and means for establishing a third communication path between at least one computational subsystem and a video processor such that any of the plurality of computational subsystems and any of the plurality of video processors may exchange information.
Claim 16
Dependent Claim
178 words
A computing system capable of efficiently carrying out a plurality of processes necessary to generate computer graphic images, the system comprising: a plurality of computational subsystems, each computational subsystem adapted to carry out a computer graphics computation task, each computational subsystem including an input and an output; a first digital communication ring, the first communication ring connected the input and output of all the computational subsystems and providing communication among the computational subsystems; a plurality of video processors, each video processor capable of storing at least a portion of a video image frame; a second digital communication ring, the second communication ring connected to all of the video processors and providing communication among the video processors; means for interfacing an external computer with the first communication ring; means for interfacing a video image peripheral device with the second communication ring; and means for establishing a third communication path between at least one computational subsystem and a video processor such that any of the plurality of computational subsystems and any of the plurality of video processors may exchange information.
Claim 17
Dependent Claim
38 words
A computing system as defined in claim 14 wherein each computational subsystem comprises means for storing a packet of data, the means for storing a packet of data connected the input and the output of the computational subsystem.
Claim 18
Dependent Claim
20 words
A computing system as defined in claim 15 wherein the means for storing a packet comprises a first-in-first-out memory structure.
Claim 19
Dependent Claim
36 words
A computing system as defined in claim 15 wherein each computational subsystem comprises means for comparing a destination address portion of the packet to a preselected bit pattern and asserting a signal if a match occurs.
Claim 20
Dependent Claim
29 words
A computing system as defined in claim 15 wherein each computational subsystem comprises transfer of a packet from a first computational subsystem for synchronizing to a second computational subsystem.
Claim 21
Dependent Claim
16 words
A computing system as defined in claim 15 wherein the output comprises a transparent latch circuit.
Claim 22
Dependent Claim
55 words
A computing system as defined in claim 15 wherein data is transmitted on the first digital communication ring in packets of less than a maximum length and wherein the packet comprises a trip count word portion, the computational subsystem comprising means for decrementing the trip count word portion as the packet passes through the interface.
Claim 23
Dependent Claim
27 words
A computing system as defined in claim 20 wherein the means for decrementing further comprises means for indicating when the trip count word has decremented to zero.
Claim 24
Dependent Claim
31 words
A computing system as defined in claim 14 the computational subsystems each further comprise means for inputting a packet of data of preferably 1024 words onto the first digital communication ring.
Claim 25
Dependent Claim
22 words
A computing system as defined in claim 14 wherein the means for interfacing an external computer comprises a first communication ring controller.
Claim 26
Dependent Claim
34 words
A computing system as defined in claim 14 wherein the means for interfacing a host computer means for receiving a digital time code and means and receiving machine control signals to control peripheral devices.
Claim 27
Dependent Claim
34 words
A computing system as defined in claim 24 wherein the means for interfacing an external computer further comprises means for receiving information from the host computer by both serial bus and a communication network.
Claim 28
Dependent Claim
23 words
A computing system as defined in claim 1 or claim 14 wherein each computational subsystem includes a microprocessor and a programmable hardware booster.
Claim 29
Dependent Claim
43 words
A computing system as defined in claim 1 or claim 14 wherein the plurality of video processors each have parallel input and a parallel output, each parallel input and output being adapted to exchange a component digital video signal with another video processor.
Claim 30
Dependent Claim
25 words
A computing system as defined in claim 27 further comprising means for synchroneously passing the component digital video signal between the plurality of video processors.
Claim 31
Dependent Claim
23 words
A computing system as defined in claim 1 or claim 14 wherein the plurality of video processors comprise a plurality of frame buffers.
Claim 32
Dependent Claim
51 words
A computing system as defined in claim 29 wherein each of the plurality of frame buffers comprises: means for receiving commands placed on the second communication ring; means for storing at least one frame of a component digital video signal; and means for outputting a video signal to a peripheral device.
Claim 33
Dependent Claim
30 words
A computing system as defined in claim 30 wherein the means for outputting a video signal comprises means for outputting a RGB analog video signal to an external color monitor.
Claim 34
Dependent Claim
63 words
A computing system as defined in claim 1 or claim 14 wherein the means for interfacing a video image peripheral device with the second communication ring or the means exchanging information between a video device and the second communication ring comprises means for receiving at least one video signal input and organizing a video signal train for transmission on the second communication ring.
Claim 35
Dependent Claim
44 words
A computing system as defined in claim 32 wherein the means for interfacing a video image peripheral device and the second communication ring further comprises means for generating commands and addressing those commands to other digital video processors located on the second communication ring.
Claim 36
Dependent Claim
50 words
A computing system as defined in claim 33 wherein the means for interfacing a video image peripheral device further comprises means for placing information from a first peripheral video device onto the second communication ring and for passing information from the second communication ring to a second, peripheral video device.
Claim 37
Dependent Claim
55 words
A computing system as defined in claim 14 wherein the means for establishing a third communication path comprises a local bus interconnecting the means for interfacing an external computer with the means for interfacing a video image peripheral device such that data may be passed between the first communication ring and the second communication ring.
Claim 38
Dependent Claim
31 words
A computing system as defined in claim 1 or claim 14 further comprising a plurality of local communication pathways, each local communication pathway interconnecting each video processor with one computational subsystem.
Claim 39
Dependent Claim
37 words
A computing system as defined in claim 1 or claim 14 further comprising a plurality of workstations, each workstation having a communication link with one computational subsystem whereby a user may input data to the computational subsystem.
Claim 40
Independent Claim
166 words
A system for distributing video signals among at least a first, second, and third video processor, the system comprising: a parallel ring input provided on each video processor; a parallel ring output provided on each video processor, the ring outputs connected to the ring input of the adjacent downstream video processor such that a video communication ring is formed, each video processors capable of processing a video signal from its ring input to its ring output in real time; means for synchronizing the operation of each of the video processors with other video processors; means for inserting a video signal obtained from at least one peripheral video device onto the video communication ring; and means for storing a video signal which has been passed downstream from the third video processor to the first video processor and for reinserting the video signal onto the video communication ring such that the video signal may be passed to the second video processor located upstream from the third video processor.
Claim 41
Independent Claim
166 words
A system for distributing video signals among at least a first, second, and third video processor, the system comprising: a parallel ring input provided on each video processor; a parallel ring output provided on each video processor, the ring outputs connected to the ring input of the adjacent downstream video processor such that a video communication ring is formed, each video processors capable of processing a video signal from its ring input to its ring output in real time; means for synchronizing the operation of each of the video processors with other video processors; means for inserting a video signal obtained from at least one peripheral video device onto the video communication ring; and means for storing a video signal which has been passed downstream from the third video processor to the first video processor and for reinserting the video signal onto the video communication ring such that the video signal may be passed to the second video processor located upstream from the third video processor.
Claim 42
Dependent Claim
38 words
A system for distributing video signals as defined in claim 38 wherein the means for inserting a video signal comprises means for generating a video signal train corresponding to a video signal obtained form a peripheral video device.
Claim 43
Dependent Claim
36 words
A system for distributing video signals as defined in claim 39 wherein the means for generating a video signal train comprises means for generating a command portion and a pixel portion of the video signal train.
Claim 44
Dependent Claim
28 words
A system for distributing video signals as defined in claim 39 wherein the means for generating a video signal comprises means for generating a component digital video signal.
Claim 45
Dependent Claim
49 words
A system for distributing video signals as defined in claim 41 wherein the ring input and the ring output each comprise four bytes of conductors, the first, second, third, and fourth bytes, capable of carrying the red, blue, green, and key components, respectively, of a component digital video signal.
Claim 46
Dependent Claim
45 words
A system for distributing video signals as defined in claim 40 wherein the means for generating a video signal train comprises means for generating commands in the command portion of the video signal train and wherein each video processor comprises means for receiving the commands.
Claim 47
Dependent Claim
30 words
A system for distributing video signals as defined in claim 38 wherein each video processor comprises a video memory capable of holding at least one frame of the video signal.
Claim 48
Dependent Claim
38 words
A system for distributing video signals as defined in claim 44 wherein each video processor comprises means for outputting a video image received at the ring input or stored in the video memory to an analog video device.
Claim 49
Dependent Claim
39 words
A system for distributing video signals as defined in claim 38 wherein the means for synchronizing comprises means for selectively synchronizing the operation of each of the video processors between a house synchronization signal and a ring synchronization signal.
Claim 50
Dependent Claim
54 words
A system for distributing video signals as defined in claim 38 wherein the means for inserting a video signal comprises means for obtaining a video signal from one of at least two peripheral video devices and means for outputting a video signal from the video communication ring to at least one peripheral video device.
Claim 51
Dependent Claim
72 words
A system for distributing video signals as defined in claim 38 wherein the video signal placed on the video communication ring is partitioned into video signal trains, each video signal train including the pixel data for one line of a video image, the means for storing comprising means for storing the pixel data for one line of a video image and for synchroneously reinserting the pixel data onto the video communication ring.
Claim 52
Independent Claim
153 words
A method of processing a digital video signal in a video processing system which includes a plurality of digital video processors, the method comprising the steps of: inputting the digital video signal to a first video processor; passing the digital video signal to a second digital video processor in real time; passing the digital video signal onto a last video processor in real time; controlling the passing of the digital video signal from one video processor to the next so that the digital video signal arrives at the desired video processor; outputting a video signal to an external video device at any one of the video processors; selectively passing the output from the last video processor to a storage buffer; and inserting the contents of the storage buffer into the input of the first video processor thereby allowing any video processor to pass a digital video signal to another video processor located upstream.
Claim 53
Independent Claim
153 words
A method of processing a digital video signal in a video processing system which includes a plurality of digital video processors, the method comprising the steps of: inputting the digital video signal to a first video processor; passing the digital video signal to a second digital video processor in real time; passing the digital video signal onto a last video processor in real time; controlling the passing of the digital video signal from one video processor to the next so that the digital video signal arrives at the desired video processor; outputting a video signal to an external video device at any one of the video processors; selectively passing the output from the last video processor to a storage buffer; and inserting the contents of the storage buffer into the input of the first video processor thereby allowing any video processor to pass a digital video signal to another video processor located upstream.
Claim 54
Dependent Claim
62 words
A method of processing a digital video signal as defined in claim 49 wherein the step of inputting the digital video signal comprises the steps of: generating a component digital video signal corresponding to the video signal; and generating a video signal train, containing the component digital video signal, the video signal train including a command portion and a pixel data portion.
Claim 55
Dependent Claim
56 words
A method of processing a digital video signal as defined in claim 50 further comprising the steps of: receiving the command portion of the video signal train at a video processor; determining if the command contained in the command portion is addressed to the video processor; and carry out the command by the addressed video processor.
Claim 56
Dependent Claim
58 words
A method of processing a digital video signal as defined in claim 49 wherein the step of passing the digital video signal to a second digital video processor in real time comprises the step of passing the equivalent of one frame of pixel data to the second digital video processor within one frame of the appropriate video standard.
Claim 57
Dependent Claim
48 words
A method of processing a digital video signal as defined in claim 49 wherein the step of selectively passing the output of the last video processor comprises the step of selectively passing at least one line of pixel data from the digital video signal to the storage buffer.
Claim 58
Dependent Claim
55 words
A method of processing a digital video signal as defined in claim 53 wherein the step of inserting the contents of the storage buffer comprises the step of generating a video signal train containing the pixel data contained in the storage buffer and passing the video signal train to the adjacent downstream digital video processor.
Claim 59
Dependent Claim
46 words
A method of processing a digital video signal as defined in claim 49 wherein the step of controlling the passing of the digital video signal comprises the step selectively synchronizing the passing of the digital video signal with a house standard or a video processor standard.
Claim 60
Dependent Claim
40 words
A method of processing a digital video signal as defined in claim 49 wherein the step of outputting a video signal at anyone of the video processors comprises the step of outputting an analog video signal to a video monitor.
References Cited (Backward Citations)
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