An ultra dense DRAM cell array and its method of fabrication

Claim 2

A process for forming an ultra dense dynamic random access memory array comprising the steps of providing a first semiconductor substrate (21) of a first conductivity type having a region (22) of second conductivity type extending from the surface of said first substrate partially into said first substrate (21), said first substrate (21) being disposed over a second substrate (8) of first conductivity type and spaced from said first substrate (21) by a layer (20) of insulation, forming a first plurality of insulation filled trenches (17) (25) which extend from said surface into said second substrate (8) leaving a plurality of spaced apart upstanding regions consisting of portions of said first (21) and second substrates (8) and said insulation layer (20), forming a second plurality of trenches (32) in said plurality of upstanding regions which extend from said surface into said second substrate (8) leaving a plurality of device regions (4) (5) and simultaneously forming a third plurality of trenches in said insulation filled trenches (17) (25) each of said third plurality of trenches being disposed between a pair of trenches (32) of said second plurality of trenches (32) and extending partially into said insulation filled trench (17) (25) to a given depth, refilling said second (32) and third plurality of trenches with conductive material (11,12), forming a fourth plurality of trenches in selected of said second plurality of trenches (32) filled with conductive material (11) to a depth greater than said given depth, forming insulation (10) at the bottom of each of said fourth plurality of trenches to a thickness sufficient to raise the level of each of said fourth plurality of trenches to said given depth providing with the bottoms of said third plurality of trenches a plurality of insulating gate conductor channels extending orthogonally with respect to said insulation filled trenches (17) (25).

Claim 3

A process according to claim 1 further including the steps forming a pair of gate conductors (6) in each of said channels in insulated spaced relationship with adjacent device regions (4), depositing insulating material (15) in each of said channels to electrically isolate the gate conductors (6) in each channel from each other, introducing a first conductivity type dopant region (3) into said region of second conduc­tivity type (4) in each of said device regions (4) (5), planarizing said insulating material (15), and forming a plurality of conductors (16) disposed in orthogonal relationship with said gate con­ductors (6) each of said conductors (16) contacting a plurality of said first conductivity type dopant regions (3).

Claim 4

A process according to claim 1 or 2 wherein the step of forming a first plurality of insulation filled trenches includes the steps of: masking the surface of said first semiconductor substrate to expose portions of said surface, etching said substrate to form said plurality of trenches and chemically vapor depositing said insulation into said first plurality of insulation filled trenches.

Claim 5

A process according to anyone of the claims 1 to 3 wherein the step of forming a second plurality of trenches and simultaneously forming a third plurality of trenches includes the steps of: forming layers of a nitride, oxide and a nitride in that order on said surface and over said insulation filled trenches, patterning said last mentioned nitride layer leaving spaced apart nitride masking regions, depositing a layer of polycrystalline semi­conductor conformally over said spaced apart nitride regions and reactively ion etching said polycrystalline semiconductor to form sidewall spacers on the sides of each of said spaced apart nitride masking regions, removing said spaced apart masking regions, patterning said first mentioned nitride layer and said oxide layer to expose surface portions of said substrate and said insulation filled trenches, and, reactively ion etching said exposed surface portion of said substrate and said insulation filled trenches to form said second and third plurality of trenches simultaneously.

Claim 6

A process according to anyone of the claims 1 to 4 wherein the step of refilling said trenches with conductive material includes the steps of: forming a composite oxide-nitride layer and a protective layer of polycrystalline semiconductor in said second plurality of trenches, subjecting said second plurality of trenches to reactive ion etching to remove said protective layer of polycrystalline layer from said second plurality of trenches and said composite oxide-­nitride layer from the bottoms of said second plurality of trenches, depositing polycrystalline semiconductor material in said second and third plurality of trenches and, polishing said semiconductor material to planarize the surface of said memory array.

Claim 7

A process according to anyone of the claims 1 to 5 wherein the step of forming a fourth plurality of trenches is selected of said second plurality of trenches filled with conductive material includes the steps of: reactively ion etching said selected of said second plurality of trenches to form said fourth plurality of trenches in said conductive material.

Claim 8

A process according to anyone of the claims 1 to 6 wherein the step of forming insulation at the bottom of each of said fourth plurality of trenches includes the step of oxidizing the topmost portion of said conductive material.

Claim 9

A process for fabricating an ultra dense DRAM memory array comprising the steps of: forming a first plurality of trenches in a semiconductor substrate which is spaced from an underlying substrate by an insulating layer which extends through said semiconductor substrate and said insulating layer into said underlying substrate said trenches having a given depth and extending in a given direction, refilling said plurality of trenches with an insulating material, forming a second plurality of trenches in said semiconductor substrate through said semiconductor substrate and said insulating layer into said underlying substrate to said given depth leaving a plurality of active device regions and simul­ taneously excavating portions of said insulating material from said first plurality of trenches between said second plurality of trenches to a depth less than said given depth, refilling said second plurality of trenches and said excavated portions of said first plurality of trenches with a conductive material, removing said conductive material from said excavated portions of said first plurality of trenches to expose the surfaces of said insulating material therein and from selected of said second plurality of said refilled trenches to a depth below said depth less than said given depth to form a plurality of flat topped regions of said con­ductive and said insulating materials which extend in a direction orthogonal to said given direction, oxidizing said plurality of flat topped regions of conductive material such that the tops of the resulting insulating oxide are at the same level as the tops of said flat topped regions of insulating material forming a plurality of gate conduits extending in a direction orthogonal to said given direction, forming a pair of conductive gate elements in each of said gate conduits each of said conductive gate elements being disposed in insulted spaced relationship with adjacent active device regions of said plurality of active device regions.

Claim 10

A process for fabricating an ultra dense DRAM memory array comprising the steps of: forming a first plurality of trenches in a semiconductor substrate which is spaced from an underlying substrate by an insulating layer which extends through said semiconductor substrate and said insulating layer into said underlying substrate said trenches having a given depth and extending in a given direction, refilling said plurality of trenches with an insulating material, forming a second plurality of trenches in said semiconductor substrate through said semiconductor substrate and said insulating layer into said underlying substrate to said given depth leaving a plurality of active device regions and simul­ taneously excavating portions of said insulating material from said first plurality of trenches between said second plurality of trenches to a depth less than said given depth, refilling said second plurality of trenches and said excavated portions of said first plurality of trenches with a conductive material, removing said conductive material from said excavated portions of said first plurality of trenches to expose the surfaces of said insulating material therein and from selected of said second plurality of said refilled trenches to a depth below said depth less than said given depth to form a plurality of flat topped regions of said con­ductive and said insulating materials which extend in a direction orthogonal to said given direction, oxidizing said plurality of flat topped regions of conductive material such that the tops of the resulting insulating oxide are at the same level as the tops of said flat topped regions of insulating material forming a plurality of gate conduits extending in a direction orthogonal to said given direction, forming a pair of conductive gate elements in each of said gate conduits each of said conductive gate elements being disposed in insulted spaced relationship with adjacent active device regions of said plurality of active device regions.

Claim 11

A process according to claim 8 further including the steps of: forming flat topped insulation in said gate conduits to electrically isolate each one of said pairs of conductive gate elements from each of the other of said pairs of conductive gates, implanting said plurality of device regions with a conductivity type determining impurity to form a plurality of implanted device regions, and depositing and patterning a plurality of con­ductive lines extending in said given direction each of which contacts a number of said plurality of implanted device regions.

Claim 12

A process for forming an ultra dense dynamic random access memory array comprising the steps of: forming a first plurality of insulation filled trenches in a semiconductor substrate of first height, forming a second plurality of trenches ortho­gonally with said first plurality of trenches in said substrate and in portions of said insulation filled trenches leaving a plurality of semicon­ductor regions of first height with gaps there­between and a plurality of insulator regions of a second height less than said first height disposed between said insulator regions of said first height, refilling said second plurality of trenches such that selected of said gaps are partially filled with conductive and insulating material in that order exposing portions of said semiconductor regions extending above said partially filled gaps, the latter having a height equal to said second height, and forming a plurality of conductive gates ortho­gonal to said first plurality of trenches each said gate being disposed in insulated spaced relationship with a number of said exposed portions of said semiconductor regions and extending over said partially filled gaps and said insulator regions of said second height.

Claim 13

A process for forming an ultra dense dynamic random access memory array comprising the steps of: forming a first plurality of insulation filled trenches in a semiconductor substrate of first height, forming a second plurality of trenches ortho­gonally with said first plurality of trenches in said substrate and in portions of said insulation filled trenches leaving a plurality of semicon­ductor regions of first height with gaps there­between and a plurality of insulator regions of a second height less than said first height disposed between said insulator regions of said first height, refilling said second plurality of trenches such that selected of said gaps are partially filled with conductive and insulating material in that order exposing portions of said semiconductor regions extending above said partially filled gaps, the latter having a height equal to said second height, and forming a plurality of conductive gates ortho­gonal to said first plurality of trenches each said gate being disposed in insulated spaced relationship with a number of said exposed portions of said semiconductor regions and extending over said partially filled gaps and said insulator regions of said second height.

Claim 14

A process according to claim 10 further including the steps of insulating adjacent gates from each other, doping a portion of each portion of said semicon­ductor region extending above said partially filled gap to form a region of opposite conductivi­ty type therein, and forming a plurality of conductive interconnections each said interconnection being connected to a plurality of said opposite conductivity regions and extending in the same direction as said first plurality of trenches.

Claim 15

A process according to claim 10 or 11 wherein said substrate includes a first layer of semicon­ductor material of first conductivity type having a region of second conductivity type extending from its surface partially into said first layer, said first layer being disposed over a second layer of said first conductivity type and spaced from said first layer by a layer of insulating material.

Claim 16

An ultra dense dynamic random access memory array comprising: a conductive substrate (8)(11)(12) having a plurality of rows of single crystal semiconductor devices (2) disposed in insulated spaced relation­ship with said substrate (8)(11)(12) said substrate having insulation (10) covered portions (11) which extend between pairs of devices (2) in each row and between insulation regions (17′) rows of which are disposed between said rows of semicon­ductor devices (2), the tops of said insulation regions (17′) being level with the tops of said insulation (10) covered portions (11) forming a plurality of gate conduits perpendicular to said rows of semiconductor devices (2), a pair of gate electrodes (6) disposed in each of said gate conduits, each of said pair of gate electrodes being in insulated spaced relationship with the other of said pair and with a portion (4) of each of said semiconductor devices (2) in an associated column of said semiconductor devices (2), and a plurality of conductive lines (16) disposed orthogonally with said gate electrodes (6) each of said lines contacting another portion (3) of each of said semiconductor devices (2) arranged in the same row.

Claim 17

An ultra dense dynamic random access memory array comprising: a conductive substrate (8)(11)(12) having a plurality of rows of single crystal semiconductor devices (2) disposed in insulated spaced relation­ship with said substrate (8)(11)(12) said substrate having insulation (10) covered portions (11) which extend between pairs of devices (2) in each row and between insulation regions (17′) rows of which are disposed between said rows of semicon­ductor devices (2), the tops of said insulation regions (17′) being level with the tops of said insulation (10) covered portions (11) forming a plurality of gate conduits perpendicular to said rows of semiconductor devices (2), a pair of gate electrodes (6) disposed in each of said gate conduits, each of said pair of gate electrodes being in insulated spaced relationship with the other of said pair and with a portion (4) of each of said semiconductor devices (2) in an associated column of said semiconductor devices (2), and a plurality of conductive lines (16) disposed orthogonally with said gate electrodes (6) each of said lines contacting another portion (3) of each of said semiconductor devices (2) arranged in the same row.

Claim 18

A dynamic random access memory array according to claim 13 wherein said semiconductor devices are field effect transistors.

Claim 19

A dynamic random access memory array according to claim 13 or 14 wherein said a portion (4) of said semiconductor device is the channel region of a field effect transistor, and wherein said another portion (3) of said semiconductor device is a source region of said field effect transistor.