Memory management in packet data mode systems

Claim 2

A memory management system for a Packet Data Mode System used in conjunction with a Direct Memory Access DMA controller, the management system of the type for extracting and sending a message from a memory storage or receiving and storing the message to the memory storage where each message has a Control/Address Field (CAF), and may have a Data Field (DF), the improvement comprising: a. means for generating a change of field signal; b. means for communicating said change of field signal to said DMA controller; c. means for generating an end of message signal; and d. means for communicating said end of message signal to said DMA controller, whereby said CAF and said DF are stored separately from one another.

Claim 3

The memory management system according to Claim 1 wherein said memory management system is further used in conjunction with a central processing unit (CPU), said system further comprising means for chaining at least two complete messages together without requiring the intervention of said CPU for uninterrupted data transmission.

Claim 4

The memory management system according to Claim 2 wherein said DMA controller has DMA registers which can be updated after transmission of a chained message.

Claim 5

The memory management system according to Claim 2 further comprising means for indicating locations in memory where said CAF and DF are stored.

Claim 6

The memory management system according to Claim 4 wherein said means for indicating comprises a plurality of vectors.

Claim 7

The memory management system according to Claim 5 further comprising an address pointer logic for use by the CPU to determine which of the vectors is in use.

Claim 8

The memory management system according to Claim 6 further comprising means for instructing the CPU to update an appropriate one of said vectors.

Claim 9

The memory management system according to Claim 7 wherein said means for instructing comprises a valid address logic indicator having a first condition and a second condition for instructing the CPU to update said appropriate one of said vectors having a valid logic indicator in said second condition.

Claim 10

The memory management system according to Claim 8 further comprising means for determining if a DF is present.

Claim 11

The memory management system according to Claim 1 wherein said system is for use with an HDLC system.

Claim 12

The memory management system according to Claim 10 wherein said HDLC system is an ISDN system.

Claim 13

The memory management system according to Claim 1 wherein a single DF may be appended to multiple CAF.

Claim 14

The memory management system according to Claim 1 wherein multiple DF may be appended to a single CAF.

Claim 15

A memory management system for a Packet Data Mode System for communicating a message, each said message having a control/address field (CAF) and may have a data field (DF), comprising: a. an HDLC controller; b. a Direct Memory Access DMA controller having DMA registers; c. a CPU; d. means for generating a change of field signal in said HDLC controller; e. means for communicating said change of field signal from said HDLC controller to said DMA controller; f. means for generating an end of message signal in said HDLC controller; g. means for communicating said end of message signal from said HDLC controller to said DMA controller, h. means for chaining two or more messages together thereby forming a chained message without intervention by the CPU; i. means for updating said DMA registers after transmission of said chained message; j. a plurality of vectors for indicating an address in memory where CAF and DF are stored; k. means for determining which of the vectors is in use; 1. means for instructing the CPU to update an appropriate one of said vectors; and m. means for determining if a DF is present, whereby said CAF and said DF are stored separately from one another.

Claim 16

A memory management system for a Packet Data Mode System for communicating a message, each said message having a control/address field (CAF) and may have a data field (DF), comprising: a. an HDLC controller; b. a Direct Memory Access DMA controller having DMA registers; c. a CPU; d. means for generating a change of field signal in said HDLC controller; e. means for communicating said change of field signal from said HDLC controller to said DMA controller; f. means for generating an end of message signal in said HDLC controller; g. means for communicating said end of message signal from said HDLC controller to said DMA controller, h. means for chaining two or more messages together thereby forming a chained message without intervention by the CPU; i. means for updating said DMA registers after transmission of said chained message; j. a plurality of vectors for indicating an address in memory where CAF and DF are stored; k. means for determining which of the vectors is in use; 1. means for instructing the CPU to update an appropriate one of said vectors; and m. means for determining if a DF is present, whereby said CAF and said DF are stored separately from one another.