EP0365322A2
Expired / Lapsed
EP
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Method and apparatus for exception handling in pipeline processors having mismatched instruction pipeline depths
Assignee: HP Inc
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Filing: 1989-10-19
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Granted: —
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Expires: 2009-10-19
Abstract
Abstract Method and apparatus is disclosed for sequentially executing instruction words comprising parallel first and second sequences of program instructions, each instruction having independently selectable execution cycle count latencies. After the occurrence of an exception, such as may arise from a page fault, the method and apparatus of the present invention identifies any instruction, begun after the instruction which caused the exception, that has completed its execution before execution of the exception provoking instruction was inhibited. The detection of an exception causes the processor to inhibit further execution of the exception provoking instruction. Instructions which have yet to complete their execution prior to the inhibition of the exception provoking instruction, are called pending instructions, and are similarly inhibited from further execution. Subsequently, the exception is serviced and the exception inducing instruction is restarted for re-execution in the processor. According to the present invention, the pending instructions are subsequently restarted and executed in the sequence of their occurrence at the time the exception provoking instruction caused the processor to inhibit further instruction execution without re-execution of the aforementioned completed instruction. The method and apparatus according to the present invention is further applicable to computing systems having a plurality of processors, of either the same or different type, such as floating point and integer processors. When applied to systems having a plurality of processors, the method and apparatus of the present invention inhibits all such further execution plural processors upon the detection of an exception in one of the processors. In processors other than the processors serving the exception, the present invention envisions method and apparatus for generation and execution of no-op instructions until the processor servicing the exception causes the execution of the pending instructions to be re-started, at which time the other processors also re-start execution of instruction which were pending at the time further execution of the instructions was inhibited.
Inventors
- 👤 Daryl F. Kinney
- 👤 Anthony N. Drogaris
- 👤 Christopher H. Mills
- 👤 Michael Kahaiyan
- 👤 John Manton
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 23:07
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F9/3861; G06F9/3863
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
306 words
Apparatus for sequentially executing instruction words having parallel first and second sequences of program instructions having variable length execution cycle counts, including a short instruction and a long instruction which, if execution is begun before said short instruction, will continue after the execution of said short instruction is complete, comprising: a first pipeline processor for executing said first sequence of instructions, including means for detecting an exception, means for inhibiting the further execution of the instruction that caused the exception and a pending instruction after an exception is detected, means for servicing said exception, means for restarting the execution of the instruction that caused the exception, and means for restarting the execution of the pending instructions, wherein said first pipeline processor allows that completion of said short instruction and said means for inhibiting the continued execution of said long instruction begun before said completed short instruction is begun, said means for inhibiting further inhibit instructions pending at the time the execution of the long instruction is inhibited, said means for servicing services said exception, said means for restarting the execution of the instruction that caused the exception restarts the execution of the long instruction, said means for restarting the execution of pending instructions restarts the execution of said pending instructions without re-executing said completed short instruction, and a second pipeline processor for executing said first sequence of instructions including means for inhibiting further execution of instructions when the first pipeline processor execution of said long instruction is inhibited, means for restarting the execution of pending instructions when the first pipeline processor means for restarting pending instructions restarts the execution of first processor pending instructions, and means for executing no-op instructions in the time interval after the execution of said second processor instructions are inhibited and the restart of the execution of said second processor pending instructions.
Claim 2
Dependent Claim
306 words
Apparatus for sequentially executing instruction words having parallel first and second sequences of program instructions having variable length execution cycle counts, including a short instruction and a long instruction which, if execution is begun before said short instruction, will continue after the execution of said short instruction is complete, comprising: a first pipeline processor for executing said first sequence of instructions, including means for detecting an exception, means for inhibiting the further execution of the instruction that caused the exception and a pending instruction after an exception is detected, means for servicing said exception, means for restarting the execution of the instruction that caused the exception, and means for restarting the execution of the pending instructions, wherein said first pipeline processor allows that completion of said short instruction and said means for inhibiting the continued execution of said long instruction begun before said completed short instruction is begun, said means for inhibiting further inhibit instructions pending at the time the execution of the long instruction is inhibited, said means for servicing services said exception, said means for restarting the execution of the instruction that caused the exception restarts the execution of the long instruction, said means for restarting the execution of pending instructions restarts the execution of said pending instructions without re-executing said completed short instruction, and a second pipeline processor for executing said first sequence of instructions including means for inhibiting further execution of instructions when the first pipeline processor execution of said long instruction is inhibited, means for restarting the execution of pending instructions when the first pipeline processor means for restarting pending instructions restarts the execution of first processor pending instructions, and means for executing no-op instructions in the time interval after the execution of said second processor instructions are inhibited and the restart of the execution of said second processor pending instructions.
Claim 3
Independent Claim
207 words
A method of sequentially executing instruction words having parallel first and second sequences of program instructions having variable length cycle times comprising the steps of: executing said first sequence of instructions in a first pipeline processor; executing said second sequence of instructions in a second pipeline processor, beginning the execution of a long instruction in said first processor, beginning the execution of a short instruction in said first processor after said long instruction is begun; ending the execution of said short instruction in said first processor; detecting an exception in the execution of said long instruction; inhibiting the further execution of said long instruction after the exception is detected and after the completion of the execution of said short instruction; inhibiting the execution of instructions in both said first and second processors while the execution of the long instruction in said first processor in inhibited; servicing said exception; restarting in the first processor, the execution of the long instruction that caused the exception; executing no-op instructions in said second processor while said exception is serviced and the execution of said long instruction is restarted; and restarting the execution in said first and second processors of the instructions pending when the execution of said long instruction was inhibited.
Claim 4
Independent Claim
207 words
A method of sequentially executing instruction words having parallel first and second sequences of program instructions having variable length cycle times comprising the steps of: executing said first sequence of instructions in a first pipeline processor; executing said second sequence of instructions in a second pipeline processor, beginning the execution of a long instruction in said first processor, beginning the execution of a short instruction in said first processor after said long instruction is begun; ending the execution of said short instruction in said first processor; detecting an exception in the execution of said long instruction; inhibiting the further execution of said long instruction after the exception is detected and after the completion of the execution of said short instruction; inhibiting the execution of instructions in both said first and second processors while the execution of the long instruction in said first processor in inhibited; servicing said exception; restarting in the first processor, the execution of the long instruction that caused the exception; executing no-op instructions in said second processor while said exception is serviced and the execution of said long instruction is restarted; and restarting the execution in said first and second processors of the instructions pending when the execution of said long instruction was inhibited.
Claim 5
Dependent Claim
171 words
Apparatus for sequential execution of program instructions having variable execution cycle counts, comprising: pipeline processor means for sequentially receiving and executing a sequence of instructions which include a long instruction followed by a short instruction, wherein the pipeline processor completes the execution of the shorter instruction before; means for detecting an exception in the execution of an instruction; and means for servicing the detected exception, wherein the pipeline processor completes the execution of the shorter instruction before an exception is detected in a preceding long instruction, said pipeline processor includes means for inhibiting the execution of the instruction that produced the exception and the execution of instructions pending when the exception was detected after detection of the exception, said pipeline processor further includes means for first re-executing the instruction that caused the exception, and for subsequently re-executing the instructions which were pending when the exception was detected in the order which existed when the exception was detected, and wherein the shorter instruction is not re-executed when the other instructions are re-executed.
Claim 6
Dependent Claim
171 words
Apparatus for sequential execution of program instructions having variable execution cycle counts, comprising: pipeline processor means for sequentially receiving and executing a sequence of instructions which include a long instruction followed by a short instruction, wherein the pipeline processor completes the execution of the shorter instruction before; means for detecting an exception in the execution of an instruction; and means for servicing the detected exception, wherein the pipeline processor completes the execution of the shorter instruction before an exception is detected in a preceding long instruction, said pipeline processor includes means for inhibiting the execution of the instruction that produced the exception and the execution of instructions pending when the exception was detected after detection of the exception, said pipeline processor further includes means for first re-executing the instruction that caused the exception, and for subsequently re-executing the instructions which were pending when the exception was detected in the order which existed when the exception was detected, and wherein the shorter instruction is not re-executed when the other instructions are re-executed.
Claim 7
Independent Claim
119 words
A method of sequentially executing a sequence of program instructions having a variable execution length cycle count, comprising the steps of: executing the sequence of instruction in a pipeline processor, wherein the sequence of instruction includes a long instruction of which the completion of its execution occurs after the completion of a shorter instruction which occurs in the pipeline instruction; detecting an exception in said long instruction; completing the execution of said shorter instruction; inhibiting the continued execution of said long instruction and instructions pending at the time an exception is detected; servicing the exception; re-executing the long instruction; and re-executing the instructions pending at the time of execution detection, wherein the re-execution of said shorter instruction is avoided.
Claim 8
Independent Claim
119 words
A method of sequentially executing a sequence of program instructions having a variable execution length cycle count, comprising the steps of: executing the sequence of instruction in a pipeline processor, wherein the sequence of instruction includes a long instruction of which the completion of its execution occurs after the completion of a shorter instruction which occurs in the pipeline instruction; detecting an exception in said long instruction; completing the execution of said shorter instruction; inhibiting the continued execution of said long instruction and instructions pending at the time an exception is detected; servicing the exception; re-executing the long instruction; and re-executing the instructions pending at the time of execution detection, wherein the re-execution of said shorter instruction is avoided.
References Cited (Backward Citations)
No citation records indexed.
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