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EP0365188A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Central processor condition code method and apparatus

Assignee: HP Inc
•
Filing: 1989-10-06
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Granted: —
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Expires: 2009-10-06
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Abstract

Abstract A method and apparatus is disclosed for control of a central processor in response to a branch instruction using two separate, subsequently updated condition codes. Computer architecture is provided wherein the condition codes which determine the processor state result from the execution of instructions prior to the currently executing instruction. When the preceding instructions are executed, condition codes are set and maintained in a first condition code register. The first condition code is transferred to the second condition code register, and the first condition code register is updated to reflect the result of the current instruction execution. Any condition code state such as a branch used by the third instruction is based on the condition code state maintained in the second condition code register. The processor is provided with code which compiled according to the present invention, provides improved processor performance by reducing delays in instruction execution. If the current instruction is a condition code dependant instruction such as a branch instruction, this third instruction will execute based on the condition code maintained in the second condition code register.

Inventors

  • 👤 Russell Gray Barbour
  • 👤 Carl A. Soeder
  • 👤 Stephen J. Ciavaglia

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-06 13:48
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3861; G06F9/3863; G06F9/30003; G06F9/30072; G06F9/30094

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 117 words
A programmable computer, comprising: means for providing sequence program instructors according to a selectively applied sequence of address signals, wherein selected contiguous location in program storage means contain program instructions to be executed in sequence having at least one program instruction which enables a change in a condition code; and said contiguous program instructions further include a condition code responsive instruction having an offset of at least two locations subsequent to said program instructions affecting said condition code; and means for processing data according to said sequence of program instructions including condition code responsive means, wherein said contiguous program instructions are executed according to a predetermined address sequence and the state of said condition code responsive means.
Claim 2
Dependent Claim 117 words
A programmable computer, comprising: means for providing sequence program instructors according to a selectively applied sequence of address signals, wherein selected contiguous location in program storage means contain program instructions to be executed in sequence having at least one program instruction which enables a change in a condition code; and said contiguous program instructions further include a condition code responsive instruction having an offset of at least two locations subsequent to said program instructions affecting said condition code; and means for processing data according to said sequence of program instructions including condition code responsive means, wherein said contiguous program instructions are executed according to a predetermined address sequence and the state of said condition code responsive means.
Claim 3
Independent Claim 99 words
A method of executing a programmable sequence of instructions comprising the steps of: providing a sequence of program instructions according to a selectively applied sequence of address signals, said sequence of program instructions comprising at least one program instruction which sets the state of a condition code then executed; providing a condition code responsive instruction in said sequence of program instructions having an offset of at least two locations subsequent to said instructions affecting said condition code; and executing said sequence of program instructions according to a predetermined sequence of address signals and the state of said condition code.
Claim 4
Independent Claim 99 words
A method of executing a programmable sequence of instructions comprising the steps of: providing a sequence of program instructions according to a selectively applied sequence of address signals, said sequence of program instructions comprising at least one program instruction which sets the state of a condition code then executed; providing a condition code responsive instruction in said sequence of program instructions having an offset of at least two locations subsequent to said instructions affecting said condition code; and executing said sequence of program instructions according to a predetermined sequence of address signals and the state of said condition code.
Claim 5
Independent Claim 76 words
A method of compiling a computer program, comprising the steps of: providing machine code instruction in a contiguous sequence according to a higher level program command; providing machine code instructions which contend the state of condition codes in said contiguous sequence; providing machine code instructions which are responsive to said condition codes at a sequential offset of at least two machine code instructions subsequent to said machine code instructions which control the state of condition codes.
Claim 6
Independent Claim 76 words
A method of compiling a computer program, comprising the steps of: providing machine code instruction in a contiguous sequence according to a higher level program command; providing machine code instructions which contend the state of condition codes in said contiguous sequence; providing machine code instructions which are responsive to said condition codes at a sequential offset of at least two machine code instructions subsequent to said machine code instructions which control the state of condition codes.

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