EP0363567A2
Expired / Lapsed
EP
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A computer with interrupt controlled clock speed and its method of operation
Assignee: International Business Machines Corp
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Filing: 1989-06-22
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Granted: —
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Expires: 2009-06-22
Abstract
Abstract A computer includes a main processing unit having arithmetic logic, memory address control, input/output address control, and execution control. The computer also has an operating system program which includes an interrupt handler module. A variable frequency clock oscillator is disclosed which is controlled by the operating system via the execution control unit of the main processing unit. Machine level instructions in the executing program change the clock speed whenever it is necessary to keep the computer in synchronism with one of its I/O adapters or to speed up the clock when slow speed circuits are not being utilized. Clock speed is changed by the interrupt handling module. Circuits and programs, which require longer cycle times to execute properly, are placed together on interrupt levels. For example, the machine check program requiring the slowest clock speed is assigned to interrupt level 0. I/O adapters using low-speed circuitry are assigned to interrupt levels 1, 2 and 3. High speed circuitry adapters are assigned to interrupt levels 4-7. Whenever an interrupt is generated, the machine language program serving the interrupt first changes the speed of the oscillator clock to that speed defined for the interrupt level on which the interrupt was received. When the interrupt has been serviced, the oscillator clock speed is restored to that speed of the program operating on the interrupt level which has just been interrupted.
Inventors
- 👤 Benjamin Charles Antanaitis, Jr.
- 👤 William Blaine Emerson, Jr.
- 👤 Joseph Winfield St. John
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-23 15:17
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/08
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
146 words
A computer system comprising: a processing unit (11); a plurality of input/output adapter circuits (21, 23, 25) connected to said processing unit by interrupt lines (303, 305, 306), one (25) of said adapter circuits incapable of operating at a speed of others (21, 23) of said adapter circuits; a clock cycle generator (31) connected to said processing unit (11) to receive speed control instructions from said processing unit (11) and also connected to said processing unit (11) and to said adapter circuits (21, 23, 25) to provide clock cycles thereto; and means (Fig. 2, Fig. 3) associated with said processing unit (11) for responding to an interrupt from said (25) one of said adapter circuits by issuing to said clock cycle generator (31) a speed control instruction to generate clock cycles at a speed which said one (25) of said adapter circuits is capable of operating.
Claim 2
Dependent Claim
146 words
A computer system comprising: a processing unit (11); a plurality of input/output adapter circuits (21, 23, 25) connected to said processing unit by interrupt lines (303, 305, 306), one (25) of said adapter circuits incapable of operating at a speed of others (21, 23) of said adapter circuits; a clock cycle generator (31) connected to said processing unit (11) to receive speed control instructions from said processing unit (11) and also connected to said processing unit (11) and to said adapter circuits (21, 23, 25) to provide clock cycles thereto; and means (Fig. 2, Fig. 3) associated with said processing unit (11) for responding to an interrupt from said (25) one of said adapter circuits by issuing to said clock cycle generator (31) a speed control instruction to generate clock cycles at a speed which said one (25) of said adapter circuits is capable of operating.
Claim 3
Dependent Claim
58 words
The computer system of claim 1, further comprising: means (Fig. 2, Fig. 3) associated with said processing unit (11) for issuing to said clock cycle generator (31) a speed control instruction to generate clock cycles at a speed at which said clock cycle generator (31) was operating before said interrupt from said one (25) of said adapter circuits.
Claim 4
Dependent Claim
76 words
The computer system of claim 1 or 2 wherein said means (Fig. 2, Fig. 3) associated with said processing unit for responding to an interrupt further comprises: means responsive to an interrupt level on which said one (25) of said adapter circuits is connected for issuing a speed control instruction to said clock cycle generator (31) to generate clock cycles at a speed of the slowest one (25) of said adapter circuits is capable of operating.
Claim 5
Dependent Claim
98 words
The computer system of claim 3 wherein said means (Fig. 2, Fig. 3)associated with said processing unit for responding to an interrupt further comprises: means for identifying an adapter circuit (21, 23, 25) on said interrupt level on which said interrupt was received; means for determining the speed at which said one of said adapter circuits (21, 23, 25) is capable of operating; and means for issuing another speed control instruction to said clock cycle generator (31) to generate clock cycles at a speed which said one of said adapter circuits (21, 23, 25) is capable of operating.
Claim 6
Dependent Claim
182 words
The computer system of at least one of claims 1 to 4 having a variable frequency clock controlled by a value stored in a register, said computer system further comprising: said plurality of input/output adapter circuits (21, 23, 25) connecting said processing unit (11) and a memory (13) to input/output devices, said processing unit (11) executing a program on an interrupt level at a clock frequency determined by said interrupt level; first programmed instructions responsive to an interrupt from any one of said plurality of input/output adapter circuits connected on an interrupt level for storing an indication of a present value stored in said register and then changing said value in said register to another value; second programmed instructions for performing functions required by said input/output adapter circuits; third programmed instructions for retrieving said stored indication of said present value and changing said another value stored in said register back to said present value prior to returning to said previously executing program in order that said clock frequency be restored to a frequency at which it was operating when said interrupt occurred.
Claim 7
Independent Claim
142 words
A method of operating a computer system having a variable frequency clock, controlled by a value stored in a register, comprising the steps of: executing a program on an interrupt level at a clock frequency determined by said interrupt level; responding to an interrupt from any one of a plurality of input/output adapter circuits connected on an interrupt level; storing an indication of a present value stored in said register; changing said value in said register to another value determined by a level on which said interrupt was received; performing functions required by said input/output adapter circuits; retrieving said stored indication of said present value; changing said another value stored in said register back to said present value to restore said clock frequency to a frequency at which it was operating when said interrupt occurred; and returning to said previously executing program.
Claim 8
Independent Claim
142 words
A method of operating a computer system having a variable frequency clock, controlled by a value stored in a register, comprising the steps of: executing a program on an interrupt level at a clock frequency determined by said interrupt level; responding to an interrupt from any one of a plurality of input/output adapter circuits connected on an interrupt level; storing an indication of a present value stored in said register; changing said value in said register to another value determined by a level on which said interrupt was received; performing functions required by said input/output adapter circuits; retrieving said stored indication of said present value; changing said another value stored in said register back to said present value to restore said clock frequency to a frequency at which it was operating when said interrupt occurred; and returning to said previously executing program.
Claim 9
Dependent Claim
70 words
The method of Claim 6 following said step of changing said value, further comprising the steps of: identifying one of said plurality of input/output adapter circuits as the source of said interrupt; determining a speed at which said identified input/output adapter circuit is capable of operating; changing said value in said register to a value determined by said speed at which said identified input/output adapter circuit is capable of operating.
References Cited (Backward Citations)
No citation records indexed.
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