EP0363179A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Programmable die size continuous array
Assignee: Exar Corp
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Filing: 1989-10-04
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Granted: —
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Expires: 2009-10-04
Abstract
Abstract The present invention covers a semiconductor wafer for semi-custom use in which there are no scribe lines in at least one direction. Electrically isolated cells are provided throughout the wafer. The scribe lines can thus be arbitrarily placed according to an individual customer's instructions, with the isolated cells near the scribe line being covered with metalization to form a bonding pad. Preferably, scribe lines are provided in one direction, either horizontal or vertical. This allows fixed bonding pads to be placed near these scribe lines and allows special components, such as power transistors and ESD protection systems to be placed near the fixed bonding pads. This provides better silicon efficiency than the embodiment with no fixed scribe lines by simplifying the routing. The components which need to be near the bonding pads are placed there, rather than being located randomly throughout the wafer. The customer can then specify a length of a cell which has a fixed height.
Inventors
- 👤 Piccolo Giovanni Giannella
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 08:00
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
72 words
A semiconductor wafer for semi-custom integrated circuits comprising: an array of components arranged so that no areas are reserved without components for scribe lines in at least one of any two orthogonal directions; and a plurality of cell areas containing interior components, said cell areas having a perimeter isolation region for electrically isolating said interior components from other components and said cell areas having a size sufficient to support a bonding pad.
Claim 2
Dependent Claim
72 words
A semiconductor wafer for semi-custom integrated circuits comprising: an array of components arranged so that no areas are reserved without components for scribe lines in at least one of any two orthogonal directions; and a plurality of cell areas containing interior components, said cell areas having a perimeter isolation region for electrically isolating said interior components from other components and said cell areas having a size sufficient to support a bonding pad.
Claim 3
Dependent Claim
19 words
The wafer of claim 1 wherein there are no areas reserved without components for scribe lines in either direction.
Claim 4
Dependent Claim
24 words
The wafer of claim 1 wherein a plurality of fixed parallel elongate scribe areas are reserved in a first direction only for scribe lines.
Claim 5
Dependent Claim
18 words
The wafer of claim 3 further comprising a plurality of fixed bonding pads adjacent said fixed scribe areas.
Claim 6
Dependent Claim
19 words
The wafer of claim 4 further comprising a plurality of components adjacent said bonding pads for forming power transistors.
Claim 7
Dependent Claim
83 words
The wafer of claim 3 further comprising: an array of identical cells between said scribe areas arranged in at least two rows; and an elongate region parallel to said scribe area between said row of cells, said elongate region having a dimension in a direction orthogonal to said scribe areas which is less than a corresponding dimension of said rows of cells, such that said elongate region can be used for metal routing in digital applications and for forming capacitors in analog applications.
Claim 8
Dependent Claim
35 words
The wafer of claim 1 further comprising an array of identical cells, each cell including four electrically isolated transistor cell regions with internal components in each transistor cell region for forming at least one transistor.
Claim 9
Dependent Claim
22 words
The wafer of claim 7 wherein each of said cells has a width greater than a width required for a scribe line.
Claim 10
Dependent Claim
21 words
The wafer of claim 7 wherein each of said transistor cell regions occupies an area sufficient to support a bonding pad.
Claim 11
Dependent Claim
66 words
The wafer of claim 1 further comprising: an array of identical cells arranged in rows and columns; and a passivation layer defining a plurality of scribe line areas, each scribe line area being orthogonal to said rows and extending through at least a portion of at least one column of said cells and defining a plurality of variable bonding pad areas adjacent said scribe line areas.
Claim 12
Dependent Claim
23 words
The wafer of claim 10 wherein said variable bonding pad areas are in the same column of cells as said scribe line area.
Claim 13
Dependent Claim
38 words
The wafer of claim 1 wherein said cells are arranged in rows in said at least one direction so that a scribe line cut through any row of cells will be electrically isolated from adjacent rows of cells.
Claim 14
Dependent Claim
29 words
The wafer of claim 1 wherein said wafer includes a nitride layer formed between an n-epitaxial layer and an oxide layer to prevent contamination at a scribe line cut.
Claim 15
Dependent Claim
57 words
The wafer of claim 1 further comprising a plurality of electrostatic protection cells proximate said cell areas, each electrostatic protection cell comprising an elongate P region in an isolated n-epitaxial cell over a P substrate with contact openings at either side, so that said electrostatic protection cell can be either a cross-under or a vertical PNP transistor.
Claim 16
Dependent Claim
53 words
A die cut from the wafer of claims 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 or 14 having edges in at least one direction formed by scribe lines through said components and having bonding pads formed in a plurality of cell areas in cells adjacent said edges.
Claim 17
Independent Claim
125 words
A method for forming a semiconductor wafer for semi-custom integrated circuits comprising the steps of: forming an array of components arranged so that no areas are reserved without components for scribe lines in at least one of any two orthogonal directions; forming a plurality of cell areas containing interior components, said cell areas having a perimeter isolation region for electrically isolating said interior components from other components and said cell areas having a size sufficient to support a bonding pad; forming a passivation layer defining a plurality of scribe line areas through said components and forming a plurality of bonding pad areas in a plurality of said cell areas proximate said scribe line areas; and depositing metal in said scribe line and bonding pad areas.
Claim 18
Independent Claim
125 words
A method for forming a semiconductor wafer for semi-custom integrated circuits comprising the steps of: forming an array of components arranged so that no areas are reserved without components for scribe lines in at least one of any two orthogonal directions; forming a plurality of cell areas containing interior components, said cell areas having a perimeter isolation region for electrically isolating said interior components from other components and said cell areas having a size sufficient to support a bonding pad; forming a passivation layer defining a plurality of scribe line areas through said components and forming a plurality of bonding pad areas in a plurality of said cell areas proximate said scribe line areas; and depositing metal in said scribe line and bonding pad areas.
Claim 19
Dependent Claim
34 words
The method of claim 16 further comprising the steps of: forming fixed, parallel scribe line areas without components in one direction only; and forming fixed bonding pad areas adjacent said fixed scribe line areas.
Claim 20
Dependent Claim
137 words
A semiconductor wafer for semi-custom integrated circuits, comprising: a plurality of fixed parallel scribe line areas without components extending in one direction; a plurality of rows of cells extending between said fixed scribe line areas without interruption for scribe lines, at least two of said rows being between any two of said fixed scribe line areas; a plurality of fixed bonding pad areas extending in rows on either side of each of said fixed scribe areas; a plurality of electrically isolated cell areas in each of said cells, each cell area containing components for forming at least one transistor and having an area sufficient to support a bonding pad; a routing region between said two rows between said fixed scribe line areas; and a plurality of components for forming power transistors adjacent said fixed bonding pad areas.
Claim 21
Dependent Claim
137 words
A semiconductor wafer for semi-custom integrated circuits, comprising: a plurality of fixed parallel scribe line areas without components extending in one direction; a plurality of rows of cells extending between said fixed scribe line areas without interruption for scribe lines, at least two of said rows being between any two of said fixed scribe line areas; a plurality of fixed bonding pad areas extending in rows on either side of each of said fixed scribe areas; a plurality of electrically isolated cell areas in each of said cells, each cell area containing components for forming at least one transistor and having an area sufficient to support a bonding pad; a routing region between said two rows between said fixed scribe line areas; and a plurality of components for forming power transistors adjacent said fixed bonding pad areas.
Claim 22
Dependent Claim
50 words
The wafer of claim 18 further comprising: a passivation layer defining a plurality of variable scribe line areas orthogonal to said fixed scribe line areas through a portion of each of two adjacent columns of cells and defining bonding pad areas over cell areas in said adjacent columns of cells.
References Cited (Backward Citations)
No citation records indexed.
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