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EP0363176A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Word organised data processors

Assignee: International Business Machines Corp
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Filing: 1989-10-04
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Granted: —
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Expires: 2009-10-04
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Abstract

Abstract In a data processing system configured to transfer data in words and an apparatus for manipulating, in response to a single manipulation instruction, the contiguous variable length sequence of data stored in bytes including an instruction decoder for decoding a single manipulation instruction, a memory for storing data in words where each but word includes a plurality of bytes, a circuit responsive to the command signal from the instruction decoder to access a contiguous sequence of the bytes from the memory wherein the first byte of the sequence is not stored on a word boundary, and providing the byte sequence to a plurality of data processing registers wherein the first byte of the sequence is aligned with the first registered boundary. Additionally the apparatus includes the capability to provide the contiguous sequence to memory wherein the first byte of the sequence is not stored on a word boundary. The data sequence maybe specified by the number of bytes in the sequence or by a sequence terminating character.

Inventors

  • 👤 Randall Dean Groves

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-31 20:19
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30018; G06F9/30032; G06F9/30036; G06F9/30038; G06F9/38; G06F9/3802; G06F9/3816

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 80 words
A word organised data processor having a natural data flow between memory and registers in transfer units of words aligned in both memory and registers on word boundaries, wherein, to enable handling of variable length sequences of information items, each item individually shorter than a word - e.g., character strings -, apparatus is inserted between the memory and the registers, responsive to invoked individual instructions, to transfer data therebetween, word boundary aligned at the registers and variably aligned at memory.
Claim 2
Dependent Claim 80 words
A word organised data processor having a natural data flow between memory and registers in transfer units of words aligned in both memory and registers on word boundaries, wherein, to enable handling of variable length sequences of information items, each item individually shorter than a word - e.g., character strings -, apparatus is inserted between the memory and the registers, responsive to invoked individual instructions, to transfer data therebetween, word boundary aligned at the registers and variably aligned at memory.
Claim 3
Dependent Claim 104 words
A processor as claimed in claim 1, wherein the inserted apparatus includes instruction decoding means for decoding instructions and providing a command signal in response to a single manipulation instruction; means in response to a command signal from the instruction decoding means for accessing the contiguous variable length sequence of information items from the memory, the first information item of the sequence being stored in the memory without restriction, i.e., potentially not on a word boundary; and means for providing the sequence to a plurality of data processing registers, the first information item of the sequence being presented aligned on the first register boundary.
Claim 4
Dependent Claim 28 words
A processor as claimed in claim 2, wherein the apparatus further includes means for altering the positions of the information items in a word component of the sequence.
Claim 5
Dependent Claim 26 words
A processor as claimed in any preceding claim wherein each information item is the same integral sub-multiple of the processor word size - i.e., a byte.
Claim 6
Dependent Claim 23 words
A processor as claimed in claim 4, wherein the inserted apparatus includes means for comparing bytes in the sequence with a predefined byte.
Claim 7
Dependent Claim 34 words
A processor as claimed in claim 5, wherein the inserted apparatus further includes means for writing the byte sequence from the registers to the memory by updating individual byte locations in the memory means.
Claim 8
Dependent Claim 43 words
A processor as claimed in claim 6 wherein the writing means for storing the byte sequence in memory includes means for determining a predetermined byte in the registers to be the trailing byte in the last word of the register stored byte sequence.
Claim 9
Dependent Claim 31 words
A processor as claimed in claim 7, wherein the byte sequence includes either a predefined byte character specifying sequence termination or a count specifying the number of bytes in the sequence.
Claim 10
Dependent Claim 47 words
A processor as claimed in claim 8, wherein the instruction specifies a first register of a sequence of registers and the apparatus includes means for storing the byte sequence in the specified first register and sufficient of the remaining registers in the natural processor nominated sequence thereof.

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