Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
139 words
A parallel computer system using a SIMD method constituted by a controller and a plurality of processor elements, each of said processor elements having a storage means to store data to be processed, said controller controlling operation of said processor elements, and said parallel computer system performing processing of said data based on a calculation control signal transmitted from said controller, said parallel computer system comprising: a data collection means connected between said processor elements and said controller for receiving output data from said processor elements, performing a predetermined calculation, and outputting calculated data to said controller, and a calculation control means connected between said data collection means and said controller for transmitting said calculation control signal from said controller to said data calculation means to make it possible to perform said predetermined calculation in said data collection circuit.
Claim 2
Dependent Claim
139 words
A parallel computer system using a SIMD method constituted by a controller and a plurality of processor elements, each of said processor elements having a storage means to store data to be processed, said controller controlling operation of said processor elements, and said parallel computer system performing processing of said data based on a calculation control signal transmitted from said controller, said parallel computer system comprising: a data collection means connected between said processor elements and said controller for receiving output data from said processor elements, performing a predetermined calculation, and outputting calculated data to said controller, and a calculation control means connected between said data collection means and said controller for transmitting said calculation control signal from said controller to said data calculation means to make it possible to perform said predetermined calculation in said data collection circuit.
Claim 3
Dependent Claim
92 words
A parallel computer system as claimed in claim 1, wherein said data collection means comprises a plurality of gathering logic units coupled to a tree configuration having a plurality of stages, a first stage of said gathering logic unit receiving said output data from each of said processor elements, a second stage of said gathering logic unit receiving calculation data obtained from said first stage, calculation data obtained from said second stage being output to a next stage, and final calculation data obtained from a final stage being output to said controller.
Claim 4
Dependent Claim
57 words
A parallel computer system as claimed in claim 1, or 2, wherein said calculation control means comprises a plurality of control registers corresponding to a number of said stage, each of the control registers being connected by a pipe-line method, and each of the control registers sequentially outputting said calculation control signal to each of said stages.
Claim 5
Dependent Claim
34 words
A parallel computer system as claimed in claim 1 or 3, wherein said calculation control signal comprises an AND calculation signal, an OR calculation signal, a MAX/MIN calculation signal, and an ADD calculation signal.
Claim 6
Dependent Claim
106 words
A parallel computer system as claimed in claim 1, 2, or 4, wherein said gathering logic unit comprises an OR calculation circuit for performing a logic OR calculation of data output from each of said processor elements, an AND calculation circuit for performing a logic AND calculation of data output from each of said processor elements, a MAX/MIN/ADD calculation circuit for obtaining a maximum value, minimum value, or added value of data output from each of said processor elements, and a selector for selecting said OR calculation circuit, AND calculation circuit, and MAX/MIN/ADD calculation circuit, these calculation being performed in response to said calculation control signal.
Claim 7
Dependent Claim
224 words
A parallel computer system using a SIMD method constituted by a controller and a plurality of processor elements, each of said processor elements having a storage means to store data to be processed, said controller controlling operation of said processor elements, and said parallel computer system performing processing of said data based on a calculation control signal transmitted from said controller, said parallel computer system comprising: a plurality of control group, each of said control groups being constituted by a number of processor elements divided from a plurality of said processor elements, for use as an address control unit, a plurality of scheduling means, each of said scheduling means provided for one of said control groups and operatively connected to said controller, and for receiving and managing an event signal designating an address signal for data to be processed and transmitted from an adjacent control group, and a plurality of real address generation means, each of said real address generation means provided for one of said control groups and connected between said controller, said scheduling means, and said control group, for generating an address signal for data to be processed by a processor element belonging to said control group based on a base address determined by said event signal to be managed by said scheduling means and an address signal applied from said controller.
Claim 8
Dependent Claim
224 words
A parallel computer system using a SIMD method constituted by a controller and a plurality of processor elements, each of said processor elements having a storage means to store data to be processed, said controller controlling operation of said processor elements, and said parallel computer system performing processing of said data based on a calculation control signal transmitted from said controller, said parallel computer system comprising: a plurality of control group, each of said control groups being constituted by a number of processor elements divided from a plurality of said processor elements, for use as an address control unit, a plurality of scheduling means, each of said scheduling means provided for one of said control groups and operatively connected to said controller, and for receiving and managing an event signal designating an address signal for data to be processed and transmitted from an adjacent control group, and a plurality of real address generation means, each of said real address generation means provided for one of said control groups and connected between said controller, said scheduling means, and said control group, for generating an address signal for data to be processed by a processor element belonging to said control group based on a base address determined by said event signal to be managed by said scheduling means and an address signal applied from said controller.
Claim 9
Dependent Claim
66 words
A parallel computer system as claimed in claim 6, wherein each of said control groups further comprises a plurality of pseudo processor elements, each pseudo processor element being connected to each processor element located in a boundary of an adjacent control group, and for transmitting data at data address to be handled by said processor element to the processor element belonging to said adjacent control group.
Claim 10
Dependent Claim
57 words
A parallel computer system as claimed in claim 6 or 7, wherein each said processor element and said pseudo processor element further comprise external memories to store read and write data, said write data being simultaneously written into said external memory of said pseudo processor element when said processor element writes data into its own external memory.
Claim 11
Dependent Claim
33 words
A parallel computer system as claimed in claim 8, wherein memory space of said external memory of said processor element is divided into a plurality of memory spaces (windows) of virtual processor elements.
Claim 12
Dependent Claim
70 words
A parallel computer system as claimed in claim 9, wherein each of said windows comprises a window number as a base address, said virtual processor element comprises a virtual processor element address as a relative address, and a real address of said processor element is obtained by adding said base address to said relative address or by performing a logical OR operation between said base address and said relative address.