EP0360153A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Oblivious memory computer networking
Assignee: Princeton University
•
Filing: 1989-09-14
•
Granted: —
•
Expires: 2009-09-14
Abstract
Abstract Independent heterogeneous computers are interconnected for oblivious, high speed, long distance communications. A printed circuit board with onboard RAM repeats all write commands through a data transmission media to a remote system. Each read and write cycle of the communicating computer is completed locally (using only local RAM). Apart from repeating write commands to a remote system, the invention is oblivious to the remote system. Data is transmitted from one machine to another without expensive communication protocols or transmission line latency induced wait states. A remote computer accesses network data only after it has been transmitted and stored in local memory. Multiple data transfers can be pipelined, that is, multiple datum may simultaneously reside in a high latency network/long transmission line. Although the time required to transmit any single datum remains proportional to the signal propagation delay, the time required to transmit multiple data is significantly reduced. Geographic separation, high speed transmission lines, low speed transmission lines, alternative means for data transmission, fault tolerance, one-way communications, multi-way communications, and high security can be supported by a single computer network of heterogeneous machines.
Inventors
- 👤 Jonathan S. Sandberg
- 👤 Richard J. Lipton
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 09:35
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/17
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
88 words
A network communications apparatus for communicating between a first computer including a first processor connected to a first memory and at least a second computer including a second processor connected to a second memory, in which said first computer is connected to said second computer by a data communications network, said improvement comprising: a first write means located in said first computer for writing information into said first memory and substantially simultaneously transmitting said information over said data communications network to said second memory of said second computer.
Claim 2
Dependent Claim
88 words
A network communications apparatus for communicating between a first computer including a first processor connected to a first memory and at least a second computer including a second processor connected to a second memory, in which said first computer is connected to said second computer by a data communications network, said improvement comprising: a first write means located in said first computer for writing information into said first memory and substantially simultaneously transmitting said information over said data communications network to said second memory of said second computer.
Claim 3
Dependent Claim
83 words
The apparatus of Claim 1 wherein said first and second memories are divided into a plurality of first and second buffers respectively such that said first write means writes substantially simultaneously to at least one of said first buffers and one of said second buffers respectively, said apparatus further comprising: a first flag generating means included in said first computer for generating a signal each time a first buffer is substantially filled with information and for transmitting said flag to said second computer.
Claim 4
Dependent Claim
43 words
The apparatus of Claim 2 further comprising: a second write means included in said second computer for writing data into said second memory and for substantially simultaneously transmitting said data over said data communications network to said first memory of said first computer.
Claim 5
Dependent Claim
45 words
The apparatus of Claim 3 further comprising: second flag generation means included in said second computer for generating a flag signal when at least one of its second buffers are substantially filled and for substantially simultaneously transmitting a generated flag signal to said second computer.
Claim 6
Dependent Claim
48 words
The apparatus of Claim 4 further comprising: first interface means located in said first computer and located between said first write means and said data communications network; and, second interface means located in said second computer and located between said second write means and said data communications network.
Claim 7
Dependent Claim
63 words
The apparatus of Claim 5 wherein said first write means, said first flag generating means, said first memory and said first interface are mounted on a board that is selectively connectable to said first computer; and, said second write means, said second flag means, said second memory and said second interface are mounted on a second board selectively connectable to said second computer.
Claim 8
Dependent Claim
56 words
The apparatus of Claim 6 wherein said first and second write means each transmit data and the respective memory address of said data to said first and second memories respectively and substantially simultaneously transmit said data and the respective memory address of said data to said second and first memories respectively over said data communications network.
Claim 9
Independent Claim
86 words
A method for communicating between a first computer including a first microprocessor connected to a first memory and a second computer including a second microprocessor connected to a second memory, in which said first computer is connected to said second computer by a data communications network, said method comprising the steps of: writing data into said first memory; and, substantially simultaneously transmitting the data to the second memory of said second computer, wherein, the second memory is oblivious to the first memory of said first computer.
Claim 10
Independent Claim
86 words
A method for communicating between a first computer including a first microprocessor connected to a first memory and a second computer including a second microprocessor connected to a second memory, in which said first computer is connected to said second computer by a data communications network, said method comprising the steps of: writing data into said first memory; and, substantially simultaneously transmitting the data to the second memory of said second computer, wherein, the second memory is oblivious to the first memory of said first computer.
Claim 11
Dependent Claim
68 words
The method of Claim 8 further comprising the steps of: dividing the first and second memories into a plurality of first and second buffers respectively; writing from said first computer to at least one of said first buffers; and, generating a flag in said first computer which signals the second computer when at least one of the first buffers of said first computer is substantially filled with data.
Claim 12
Dependent Claim
49 words
The method of Claim 9 further comprising the steps of: writing from said second computer to at least one of said second buffers; and, generating a flag in said second computer which signals the first computer when the second buffer of said second computer is substantially filled with data.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.