Capacitive reduction of junctions in a semiconductor device

Claim 2

A metal oxide semiconductor device having a relatively heavily doped junction disposed on either side of a gate, each said junction being of the same polarity, and a relatively low doped region with respect to said heavily doped junction disposed beneath at least one of said relatively heavily doped junctions, whereby when a potential is applied to said device, a depletion region disposed about said heavily doped junction extends outwardly from said heavily doped junction and coalesces with said relatively low doped region causing "bottom wall" capacitance to be reduced without compromising the punch through short channel character of said device.

Claim 3

The metal oxide semiconductor device of claim 1, wherein each junction is a N+ junction.

Claim 4

The metal oxide semiconductor device of claim 1, wherein each junction is a P+ junction.

Claim 5

The metal oxide semiconductor device of claim 1, wherein said device is a PMOS device.

Claim 6

The metal oxide semiconductor device of claim 1, wherein said device is a NMOS device.

Claim 7

The metal oxide semiconductor device of claim 1, wherein a relatively low doped region is disposed beneath both of said heavily doped junctions.

Claim 8

The metal oxide semiconductor device of claim 2, wherein said N+ junction is doped with arsenic.

Claim 9

The metal oxide semiconductor device of claim 7, wherein said low doped region is doped with BF₂.

Claim 10

The metal oxide semiconductor device of claim 2, wherein said low doped region is doped with BF₂.

Claim 11

In a metal oxide semiconductor device having a junction disposed on either side of a gate, said junctions having the same polarity and each being relatively heavily doped, the method of increasing the operative speed of said device by reducing "bottom wall" capacitance without compromising the punch through short channel character of said device, said method comprising the step of disposing beneath at least one of said junctions a relatively low doped region with respect to said heavily doped junction, whereby when a potential is applied to said device, a depletion region disposed about said heavily doped junction will be caused to extend outwardly from said junction and coalesce with said low doped region, thus reducing said "bottom wall" capacitance.

Claim 12

In a metal oxide semiconductor device having a junction disposed on either side of a gate, said junctions having the same polarity and each being relatively heavily doped, the method of increasing the operative speed of said device by reducing "bottom wall" capacitance without compromising the punch through short channel character of said device, said method comprising the step of disposing beneath at least one of said junctions a relatively low doped region with respect to said heavily doped junction, whereby when a potential is applied to said device, a depletion region disposed about said heavily doped junction will be caused to extend outwardly from said junction and coalesce with said low doped region, thus reducing said "bottom wall" capacitance.

Claim 13

The method of claim 10, wherein said low doped region is disposed beneath both junctions.

Claim 14

The method of claim 10, wherein said device is a PMOS device.

Claim 15

The method of claim 10, wherein said device is a NMOS device.

Claim 16

The method of claim 10, wherein each junction is a P+ junction.

Claim 17

The method of claim 10, wherein each junction is a N+ junction.

Claim 18

The method of claim 15, wherein said N+ junction is doped with arsenic.

Claim 19

The method of claim 16, wherein said low doped region is doped with BF₂.

Claim 20

The method of claim 15, wherein said low doped region is doped with BF₂.

Claim 21

In a metal oxide semiconductor device having a relatively heavily doped junction disposed on either side of a gate, the improvement comprising burying a relatively low doped region beneath at least one of said junctions in order to increase the operative speed of said device by reducing "bottom wall" capacitance without compromising the punch through, short channel character of said device.

Claim 22

In a metal oxide semiconductor device having a relatively heavily doped junction disposed on either side of a gate, the improvement comprising burying a relatively low doped region beneath at least one of said junctions in order to increase the operative speed of said device by reducing "bottom wall" capacitance without compromising the punch through, short channel character of said device.

Claim 23

The semiconductor device of claim 19, wherein said low doped region is buried beneath both junctions.