EP0358423A2
Expired / Lapsed
EP
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Buffer memory subsystem for peripheral controllers and method
Assignee: Advanced Micro Devices Inc
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Filing: 1989-09-04
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Granted: —
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Expires: 2009-09-04
Abstract
Abstract A buffer memory subsystem for a peripheral controller. A CPU is provided for initiating data transfer. A host adapter is also provided. A memory buffer is used to store data temporarily. The peripheral controller is adapted for operating in an environment having at least two data communications buses: a CPU data communications bus connected between the CPU and the peripheral controller, and a buffer data communications bus, isolated from the CPU data communications bus, and connected to the peripheral controller, to the memory buffer and to the host adapter. In this way, a mechanism is provided to allow the CPU to access the memory buffer by means of the peripheral controller.
Inventors
- 👤 Vineet Dujari
- 👤 Nicos Syrimis
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 15:15
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/06; G06F3/0601; G06F13/00; G06F13/10; G06F13/12; G06F13/122; G06F3/0628; G06F3/0655; G06F3/0656
Claims Analysis
Total Claims: 41
Claim 1
Independent Claim
100 words
A buffer memory subsystem for a peripheral controller comprising: a) a CPU for initiating data transfer; b) a host adapter; c) a memory buffer for temporarily storing data; d) a peripheral controller adapted for operating in an environment having at least two data communications buses; e) a CPU data communications bus operatively connected between said CPU and said peripheral controller for facilitating data transfer therebetween; and f) a buffer data communications bus operatively connected to said peripheral controller, to said memory buffer and to said host adapter, said buffer data communications bus being isolated from said CPU data communications bus.
Claim 2
Dependent Claim
100 words
A buffer memory subsystem for a peripheral controller comprising: a) a CPU for initiating data transfer; b) a host adapter; c) a memory buffer for temporarily storing data; d) a peripheral controller adapted for operating in an environment having at least two data communications buses; e) a CPU data communications bus operatively connected between said CPU and said peripheral controller for facilitating data transfer therebetween; and f) a buffer data communications bus operatively connected to said peripheral controller, to said memory buffer and to said host adapter, said buffer data communications bus being isolated from said CPU data communications bus.
Claim 3
Dependent Claim
25 words
The buffer memory subsystem of claim 1 wherein said peripheral controller comprises means for arbitrating buffer bus access requests for a plurality of initiating devices.
Claim 4
Dependent Claim
15 words
The buffer memory subsystem of claim 2 wherein said buffer memory is a RAM device.
Claim 5
Dependent Claim
18 words
The buffer memory subsystem of claim 2 wherein one of said plurality of initiating devices is said CPU.
Claim 6
Dependent Claim
25 words
The buffer memory subsystem of claim 2 wherein one of said plurality of devices is an internal sequencer for generating requests during error correction operations.
Claim 7
Dependent Claim
30 words
The buffer memory subsystem of claim 2 wherein one of said devices is data FIFO control logic for receiving data from and for transmitting data to a mass storage device.
Claim 8
Dependent Claim
25 words
The buffer memory subsystem of claim 3 wherein one of said plurality of devices is a refresh logic for refreshing data in said buffer memory.
Claim 9
Dependent Claim
18 words
The buffer memory subsystem of claim 2 wherein one of said plurality of devices is said host adapter.
Claim 10
Dependent Claim
13 words
The buffer memory subsystem of claim 2 further comprising: g) mass storage means.
Claim 11
Dependent Claim
17 words
The buffer memory subsystem of claim 9 wherein said mass storage means comprises a magnetic hard disk.
Claim 12
Dependent Claim
17 words
The buffer memory subsystem of claim 9 wherein said mass storage means comprises a magnetic tape device.
Claim 13
Dependent Claim
26 words
The buffer memory subsystem of claim 2 further comprising: g) a network adaptable to be connected to a plurality of data processing and data storage components.
Claim 14
Dependent Claim
19 words
The buffer memory subsystem of claim 12 wherein one of said plurality of data processing components is a CPU.
Claim 15
Dependent Claim
20 words
The buffer memory subsystem of claim 12 wherein one of said plurality of data storage components is a hard disk.
Claim 16
Dependent Claim
15 words
The buffer memory subsystem of claim 1 wherein said host adapter comprises an SCSI interface.
Claim 17
Dependent Claim
16 words
The buffer memory subsystem of claim 9 wherein said mass storage means comprises an optical disk.
Claim 18
Dependent Claim
26 words
The buffer memory subsystem of claim 16 further comprising: h) an error processor operatively connected to said buffer data communications bus for correcting optical disk errors.
Claim 19
Dependent Claim
23 words
The buffer memory subsystem of claim 1 whereby processor access of data stored in said buffer is permitted only by said peripheral controller.
Claim 20
Dependent Claim
23 words
The buffer memory subsystem of claim 1 whereby said processor has access to said host adapter only by means of said peripheral controller.
Claim 21
Dependent Claim
23 words
The buffer memory subsystem of claim 17 whereby said processor has access to said error processor only by means of said peripheral controller.
Claim 22
Dependent Claim
27 words
The buffer memory subsystem of claim 2 wherein said peripheral controller comprises a control register for identifying said host adapter, said error processor and said buffer memory.
Claim 23
Dependent Claim
25 words
The buffer memory subsystem of claim 21 wherein said peripheral controller further comprises pointer control means for identifying predetermined memory locations in said buffer memory.
Claim 24
Independent Claim
131 words
A method of allowing a CPU to access data in a memory device by means of a peripheral controlling means having a plurality of registers, the steps comprising: a) programming a CPU pointer with the address of a predetermined memory location; b) programming a pointer control register with a predetermined code; c) initiating a peripheral controller access cycle at a predetermined register location; d) initiating a CPU access cycle; e) generating a request for a bus arbiter; f) lengthening said CPU access cycle by negating a READY signal; g) sending said address of memory location to said memory device when said bus arbiter allows said CPU access cycle to be executed; h) accessing data at said addressed memory location; and i) terminating said CPU access cycle by asserting said READY signal.
Claim 25
Independent Claim
131 words
A method of allowing a CPU to access data in a memory device by means of a peripheral controlling means having a plurality of registers, the steps comprising: a) programming a CPU pointer with the address of a predetermined memory location; b) programming a pointer control register with a predetermined code; c) initiating a peripheral controller access cycle at a predetermined register location; d) initiating a CPU access cycle; e) generating a request for a bus arbiter; f) lengthening said CPU access cycle by negating a READY signal; g) sending said address of memory location to said memory device when said bus arbiter allows said CPU access cycle to be executed; h) accessing data at said addressed memory location; and i) terminating said CPU access cycle by asserting said READY signal.
Claim 26
Dependent Claim
20 words
24) The method in accordance with claim 23 wherein said data access comprises reading data stored in said memory device.
Claim 27
Dependent Claim
19 words
25) The method in accordance with claim 23 wherein said data access comprises storing data in said memory device.
Claim 28
Dependent Claim
41 words
26) The method in accordance with claim 23, the steps further comprising: j) incrementing said CPU pointer to point to the next memory location in said memory device; and k) accessing said next memory location by performing steps (c) - (i).
Claim 29
Dependent Claim
20 words
27) The method in accordance with claim 26 wherein said data access comprises reading data stored in said memory device.
Claim 30
Dependent Claim
19 words
28) The method in accordance with claim 26 wherein said data access comprises storing data in said memory device.
Claim 31
Dependent Claim
60 words
29) The method in accordance with claim 23 wherein said step (g) of sending said address of memory location to said memory device comprises sending a first set of predetermined bits of said address specified by said CPU pointer and sending a second set of predetermined bits of said address specified by said CPU in the current access cycle thereof.
Claim 32
Dependent Claim
20 words
30) The method in accordance with claim 29 wherein said data access comprises reading data stored in said memory device.
Claim 33
Dependent Claim
19 words
31) The method in accordance with claim 29 wherein said data access comprising storing data in said memory device.
Claim 34
Dependent Claim
110 words
32) A method of allowing a CPU to access data in a device register on a buffer bus, the steps comprising: a) initiating a peripheral controller access cycle at a predetermined register location; b) initiating a CPU access cycle; c) generating a request for a bus arbiter; d) lengthening said CPU access cycle; e) converting a value represented by a portion of a CPU address bus to an address of said device register when said bus arbiter allows said CPU access cycle to be executed; f) accessing data at said device register location; g) activating a select signal and an access control signal; and h) terminating said CPU access cycle.
Claim 35
Dependent Claim
110 words
32) A method of allowing a CPU to access data in a device register on a buffer bus, the steps comprising: a) initiating a peripheral controller access cycle at a predetermined register location; b) initiating a CPU access cycle; c) generating a request for a bus arbiter; d) lengthening said CPU access cycle; e) converting a value represented by a portion of a CPU address bus to an address of said device register when said bus arbiter allows said CPU access cycle to be executed; f) accessing data at said device register location; g) activating a select signal and an access control signal; and h) terminating said CPU access cycle.
Claim 36
Dependent Claim
18 words
33) The method in accordance with claim 32 wherein host adapter registers are mapped into said device register.
Claim 37
Dependent Claim
21 words
34) The method in accordance with claim 33 wherein said data access comprises reading data stored in said host adapter registers.
Claim 38
Dependent Claim
20 words
35) The method in accordance with claim 33 wherein said data access comprises storing data in said host adapter registers.
Claim 39
Dependent Claim
18 words
36) The method in accordance with claim 32 wherein error processor registers are mapped into said device register.
Claim 40
Dependent Claim
21 words
37) The method in accordance with claim 36 wherein said data access comprises reading data stored in said error processor registers.
Claim 41
Dependent Claim
20 words
38) The method in accordance with claim 36 wherein said data access comprises storing data in said error processor registers.
References Cited (Backward Citations)
No citation records indexed.
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