Digital division circuit using N/2-Bit subtractor for N subtractions

Claim 2

A digital division circuit including a first register (7) having a data shift function for temporarily storing a dividend therein, a second register (3) for temporarily storing a divisor, a third register (14) having a data shift function, and a subtractor (28), wherein the division circuit divides said dividend by said divisor in accordance with a non-restoring method, characterized by a zero detector (18) that monitoring higher-bit data of said divisor in said second register (3) and generating a signal when the monitored higher-bit data is all zero, a first multiplexer (20) connected between said second register (3) and a first input terminal of said subtractor (28) for supplying lower-bit data of said divisor to said subtractor in response to the signal from said zero detector (18) and selectively supplying lower-bit and higher-bit data of said divisor to said subtractor for each subtraction operation thereof in the absence of the signal from said zero detector (18), and a second multiplexer (24) connected between said first and third registers (7,14) on the one hand and a second input terminal of said subtractor on the other hand for supplying the contents of the third register (14) to said subtractor (28) in the presence of the signal from the zero detector (18) and selectively supplying higher-bit data of the contents of said third and first registers (14, 7) to the subtractor (28) for each subtraction thereof in the absence of the signal from said zero detector.

Claim 3

A digital division circuit as claimed in claim 1, characterized in that each of the first and second registers (7, 3) has N-bit length and the third register (14) has N/M-bit length, and in that the subtractor (28) has N/M-bit length, wherein M is an integer equal to or greater than 2 and smaller than N.

Claim 4

A division circuit comprising: an N-bit divisor register (3) for storing therein an N-bit divisor; an N-bit dividend register (7) for storing therein an N-bit dividend and capable of being shifted by one bit toward a most significant bit position thereof; an N/M-bit remainder register (14) capable of being shifted by one bit toward a most significant bit position thereof to store a bit shifted out of the most significant bit position of the dividend register (7) into a least significant bit position thereof, where M is an integer equal to or greater than 2 and smaller than N; a zero detector (18) for monitoring a higher-bit segment of the divisor in said divisor register and generating a signal indicating that the higher-­bit segment of the divisor is all "0"s; first and second N/M-bit latches (12,8;71,72); control means (20, 24, 28, 1, 36, 37, 40) including an N/M-bit subtractor, the control means being responsive to the signal from the zero detector for repeatedly subtracting a lower-bit segment of data in the divisor register (3) from data in the remainder register (14), writing an output generated from each of the subtractions into the first latch (12;71), repeatedly causing the remainder and dividend registers to effect the one-­bit shifting in response to each subtraction, causing data from the first latch to be written into the remainder register either when a "1" appears in a most significant bit position of the remainder register (14) or when a borrow bit is not generated by the subtractor, and deriving a quotient and a remainder from the dividend and remainder registers, respectively, when subtraction is repeated N times; and responsive to the absence of the signal from the zero detector for subtracting a lower-bit segment of data in the divisor register (3) from a higher-bit segment of data in the dividend register (7) and then subtracting a higher-bit segments of data in the divisor register (3) from data in the remainder register (14) in repeated sequences, writing outputs successively generated from the subtractions of each sequence into the second and first latches, respectively, causing the remainder and dividend registers to effect the one-bit shifting in response to each of said sequences, causing data from the first and second latches to be written into the remainder and dividend registers, respectively, when a borrow bit is generated by the subtractor, adding a "1" to a least significant bit position of the higher-bit segment data from the divisor register (3) in response to the borrow bit, and deriving a quotient from the dividend register and a remainder from the remainder and dividend registers when the subtraction is repeated N times; and logic gate means (34, 35) for writing a "1" into a least significant bit position of the dividend register (7) either when said "1" appears in the most significant bit position of the remainder register (14) or when said borrow bit is not generated by the subtractor.

Claim 5

A division circuit comprising: an N-bit divisor register (3) for storing therein an N-bit divisor; an N-bit dividend register (7) for storing therein an N-bit dividend and capable of being shifted by one bit toward a most significant bit position thereof; an N/M-bit remainder register (14) capable of being shifted by one bit toward a most significant bit position thereof to store a bit shifted out of the most significant bit position of the dividend register (7) into a least significant bit position thereof, where M is an integer equal to or greater than 2 and smaller than N; a zero detector (18) for monitoring a higher-bit segment of the divisor in said divisor register and generating a signal indicating that the higher-­bit segment of the divisor is all "0"s; first and second N/M-bit latches (12,8;71,72); control means (20, 24, 28, 1, 36, 37, 40) including an N/M-bit subtractor, the control means being responsive to the signal from the zero detector for repeatedly subtracting a lower-bit segment of data in the divisor register (3) from data in the remainder register (14), writing an output generated from each of the subtractions into the first latch (12;71), repeatedly causing the remainder and dividend registers to effect the one-­bit shifting in response to each subtraction, causing data from the first latch to be written into the remainder register either when a "1" appears in a most significant bit position of the remainder register (14) or when a borrow bit is not generated by the subtractor, and deriving a quotient and a remainder from the dividend and remainder registers, respectively, when subtraction is repeated N times; and responsive to the absence of the signal from the zero detector for subtracting a lower-bit segment of data in the divisor register (3) from a higher-bit segment of data in the dividend register (7) and then subtracting a higher-bit segments of data in the divisor register (3) from data in the remainder register (14) in repeated sequences, writing outputs successively generated from the subtractions of each sequence into the second and first latches, respectively, causing the remainder and dividend registers to effect the one-bit shifting in response to each of said sequences, causing data from the first and second latches to be written into the remainder and dividend registers, respectively, when a borrow bit is generated by the subtractor, adding a "1" to a least significant bit position of the higher-bit segment data from the divisor register (3) in response to the borrow bit, and deriving a quotient from the dividend register and a remainder from the remainder and dividend registers when the subtraction is repeated N times; and logic gate means (34, 35) for writing a "1" into a least significant bit position of the dividend register (7) either when said "1" appears in the most significant bit position of the remainder register (14) or when said borrow bit is not generated by the subtractor.

Claim 6

A division circuit comprising: an N-bit divisor register (3) for storing therein an N-bit divisor; an N-bit dividend register (7) for storing therein an N-bit dividend and capable of being shifted by one bit toward a most significant bit position thereof; an N/M-bit remainder register (14) capable of being shifted by one bit toward a most significant bit position thereof to store a bit shifted out of the most significant bit position of the dividend register (7) into a least significant bit position thereof, where M is an integer equal to or greater than 2 and smaller than N; a zero detector (18) for monitoring a higher-bit segment of the divisor in said divisor register and generating a signal indicating that the higher-­bit segment of the divisor is all "0"s; multiplexer means (20, 24) responsive to the signal from the zero detector for selecting a lower-bit segment of data in the divisor register (3) and data in the remainder register (14) and responsive to the absence of the signal from the zero detector for alternately selecting lower- and higher-bit segments of data in the divisor register (3) and alternately selecting a higher-bit segment of data in the dividend register (7) and data in the remainder register (14); an N/M-bit subtractor (28) for providing subtraction between the data selected by the multiplexer means in the presence of the signal from the zero detector and successively providing subtraction between the data alternately selected by the multiplexer means in the absence of the signal from the zero detector and producing a borrow bit and an N/M-bit output and adding a "1" to a least significant bit position of the higher-bit segment data from the divisor register (3) in response to the borrow bit; a first N/M-bit latch (12; 71) connected between the output of the subtractor and the input of the remainder register (14) and a second N/M-­bit latch (8; 72) connected between the output of the subtractor and the input of the dividend register (7); logic gate means (34, 35) for writing a "1" into a least significant bit position of the dividend register (7) either when a "1" appears in a most significant bit position of the remainder register (14) or when the borrow bit is not generated by the subtractor; and sequence control means (1, 36, 37, 40) programmed to perform the following steps in the presence of the signal from the zero detector: a) causing the subtractor to perform subtraction and writing an output therefrom into the first latch (12;71); b) causing the remainder and dividend registers to effect the one-bit shifting and causing data from the first latch (12;71) to be written into the remainder register (14) in response to the "1" being written into the least significant bit position of the dividend register (7); c) repeating the steps (a) and (b) N times; d) deriving a quotient and a remainder from the dividend and remainder registers, respectively, when subtraction is repeated N times by the subtractor, said control means being further programmed to perform the following steps in the absence of the signal from the zero detector. e) causing the subtractor to successively perform subtraction and writing successive outputs therefrom into the second and first latches (8; 72, 12;71), respectively; f) causing the remainder and dividend registers to effect the one-bit shifting and causing data from the first and second latches to be written into the remainder and dividend registers, respectively, in response to the "1" being written into the least significant bit postion of the dividend register (7); g) repeating the steps (e) and (f) until subtraction is repeated N times by the subtractor; and h) deriving a quotient from the dividend register and a remainder from the remainder and dividend registers after the subtraction is repeated N times.

Claim 7

A division circuit comprising: an N-bit divisor register (3) for storing therein an N-bit divisor; an N-bit dividend register (7) for storing therein an N-bit dividend and capable of being shifted by one bit toward a most significant bit position thereof; an N/M-bit remainder register (14) capable of being shifted by one bit toward a most significant bit position thereof to store a bit shifted out of the most significant bit position of the dividend register (7) into a least significant bit position thereof, where M is an integer equal to or greater than 2 and smaller than N; a zero detector (18) for monitoring a higher-bit segment of the divisor in said divisor register and generating a signal indicating that the higher-­bit segment of the divisor is all "0"s; multiplexer means (20, 24) responsive to the signal from the zero detector for selecting a lower-bit segment of data in the divisor register (3) and data in the remainder register (14) and responsive to the absence of the signal from the zero detector for alternately selecting lower- and higher-bit segments of data in the divisor register (3) and alternately selecting a higher-bit segment of data in the dividend register (7) and data in the remainder register (14); an N/M-bit subtractor (28) for providing subtraction between the data selected by the multiplexer means in the presence of the signal from the zero detector and successively providing subtraction between the data alternately selected by the multiplexer means in the absence of the signal from the zero detector and producing a borrow bit and an N/M-bit output and adding a "1" to a least significant bit position of the higher-bit segment data from the divisor register (3) in response to the borrow bit; a first N/M-bit latch (12; 71) connected between the output of the subtractor and the input of the remainder register (14) and a second N/M-­bit latch (8; 72) connected between the output of the subtractor and the input of the dividend register (7); logic gate means (34, 35) for writing a "1" into a least significant bit position of the dividend register (7) either when a "1" appears in a most significant bit position of the remainder register (14) or when the borrow bit is not generated by the subtractor; and sequence control means (1, 36, 37, 40) programmed to perform the following steps in the presence of the signal from the zero detector: a) causing the subtractor to perform subtraction and writing an output therefrom into the first latch (12;71); b) causing the remainder and dividend registers to effect the one-bit shifting and causing data from the first latch (12;71) to be written into the remainder register (14) in response to the "1" being written into the least significant bit position of the dividend register (7); c) repeating the steps (a) and (b) N times; d) deriving a quotient and a remainder from the dividend and remainder registers, respectively, when subtraction is repeated N times by the subtractor, said control means being further programmed to perform the following steps in the absence of the signal from the zero detector. e) causing the subtractor to successively perform subtraction and writing successive outputs therefrom into the second and first latches (8; 72, 12;71), respectively; f) causing the remainder and dividend registers to effect the one-bit shifting and causing data from the first and second latches to be written into the remainder and dividend registers, respectively, in response to the "1" being written into the least significant bit postion of the dividend register (7); g) repeating the steps (e) and (f) until subtraction is repeated N times by the subtractor; and h) deriving a quotient from the dividend register and a remainder from the remainder and dividend registers after the subtraction is repeated N times.

Claim 8

A division circuit as claimed in claim 4, wherein the sequence control means includes a first AND gate arranged to be enabled in response to a "1" output from to write data from the first latch into the remainder register, and a second AND gate arranged to be enabled in response to a "1" output from the logic gate means in the absence of the signal from the zero detector to write data from the second latch into the dividend register (7).

Claim 9

A division circuit as claimed in claim 4, wherein the integer M is 2, and the higher-bit segment of the data detected by the zero detector contains N/2 bits.