Finite state machine

Claim 2

A finite state machine comprising: first combinational logic creation means (1) to which a first input signal and a state variable input signal are inputted and from which a discrimination signal, a first output signal and a first state variable output signal are outputted; constant generating means (13) to which the discrimination signal is inputted and from which the second output signal and the second state variable output signal are outputted; first selection means (14a) in which the first output signal and the second output signal are selected; second selection means (14b) in which the first state variable output signal and the second state variable output signal are selected; and second combinational logic creation means (40) to which the second input signal and the discrimination are inputted and from which a selection means controlling signal is outputted; wherein the first and the second selection means are controlled by the selection means controlling signal whereby the output signal from said first selection means constitutes an output signal from the state machine and the output from the second selection means constitutes the state variable input signal.

Claim 3

A finite state machine according to claim 1, wherein said second input signal is inputted to said second combinational logic circuit and said constant generation circuit.

Claim 4

A finite state machine comprising first combinational logic generation means (1) to which the first input signal and a state variable input signal are inputted and from which a discrimination signal, the first output signal and the first state variable output signal are outputted; n (n: integer) numbers of constant generation means (13a to 13c); first selector means (14a); second selector means (14b); and second combinational logic creation means (40) to which the second input signal and the discrimination are inputted and from which a selection means controling signal is outputted; wherein the i-th constant generation means of said n numbers of constant generation means generates the (i + 1)-th output signal and the (i +1)-th state variable output signal; said first selector means selects said first to (n + 1)-th output signals whereas said second selector means selects sais first to (n + 1)-th state variable signals; said first and second selector means are controlled by said selector means control signal; and the output signal from said first selection means constitutes an output signal from the state machine and the output from the second selection means constitutes the state variable input signal.

Claim 5

A finite state machine comprising first combinational logic generation means (1) to which the first input signal and a state variable input signal are inputted and from which a discrimination signal, the first output signal and the first state variable output signal are outputted; n (n: integer) numbers of constant generation means (13a to 13c); first selector means (14a); second selector means (14b); and second combinational logic creation means (40) to which the second input signal and the discrimination are inputted and from which a selection means controling signal is outputted; wherein the i-th constant generation means of said n numbers of constant generation means generates the (i + 1)-th output signal and the (i +1)-th state variable output signal; said first selector means selects said first to (n + 1)-th output signals whereas said second selector means selects sais first to (n + 1)-th state variable signals; said first and second selector means are controlled by said selector means control signal; and the output signal from said first selection means constitutes an output signal from the state machine and the output from the second selection means constitutes the state variable input signal.

Claim 6

A finite state machine comprising: first combinational logic creation means (1) to which a first input signal and a state variable input signal are inputted and from which a discrimination signal, the first output signal and the first state variable output signal are outputted; first constant generation means (13a) for generating the second output signal; second constant generation means (13b) for generat­ing the sencond state variable output signal; first selection means (14a) for selecting said first output signal and said output signal thereby to produce a state machine output signal; second selection means (14b) for selecting said first state variable output signal and said state variable output signal thereby to generate said state variable input signal; and second combinational logic generation means (40) to which the second input signal and the discrimination are inputted and from which a selection means controlling signal is outputted; wherein said first and second selection means are controlled by said selection means control signal, and at least one of said first and second constant generation means and said second combinational logic generation means is controlled by a part of said state machine output signal.

Claim 7

A finite state machine comprising: first combinational logic creation means (1) to which a first input signal and a state variable input signal are inputted and from which a discrimination signal, the first output signal and the first state variable output signal are outputted; first constant generation means (13a) for generating the second output signal; second constant generation means (13b) for generat­ing the sencond state variable output signal; first selection means (14a) for selecting said first output signal and said output signal thereby to produce a state machine output signal; second selection means (14b) for selecting said first state variable output signal and said state variable output signal thereby to generate said state variable input signal; and second combinational logic generation means (40) to which the second input signal and the discrimination are inputted and from which a selection means controlling signal is outputted; wherein said first and second selection means are controlled by said selection means control signal, and at least one of said first and second constant generation means and said second combinational logic generation means is controlled by a part of said state machine output signal.

Claim 8

A finite state machine according to claim 1, wherein said first combinational logic generation means is a programmable logic array (PLA).

Claim 9

A finite state machine according to claim 3, wherein said first combinational logic generation means is a programmable logic array (PLA).

Claim 10

A finite state machine according to claim 4, wherein said first combinational logic generation means is a programmable logic array (PLA).