EP0356598A1
Expired / Lapsed
EP
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Digital filter for a modem sigma-delta analog-to-digital converter
Assignee: International Business Machines Corp
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Filing: 1988-08-30
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Granted: —
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Expires: 2008-08-30
Abstract
Abstract Digital filter used in a sigma-delta decoder wherein each input sample is involved in the computation of three consecutive PCM output samples. During one sigma-delta sampling period, the filter performs three parallel operations by multiplexing (44) one adder (36) running three times faster than the sigma-delta clock for loading one of three accumulators (38, 40, 42). As the analog-to-digital converter must be kept in phase with remote modem transmit clock, the PCM sampling clock is controlled by the phase tracking performed by adding or subtracting one period of the crystal oscillator from time to time to the PCM sampling clock period. Rotating the order the accumulators are loaded by the adder each PCM sampling time enables to have zero as last coefficient value to add to the accumulator the contents of which is used as PCM output samples. Thus, each PCM sample value is available in the corresponding accumulator one sigma-delta clock period before the last computation. In case of a correction which shortens or lengthens the PCM sampling period, this correction does not change the PCM sample value to be output since the last computation which is either cancelled or repeated, consists in adding zero to the previous accumulator contents.
Inventors
- 👤 Maurice Cukier
- 👤 Daniel Mauduit
- 👤 Gérard Orengo
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 00:57
CPC Classifications
H; H03; H03H; H03H17/00; H03H17/02; H03H17/06; H03H17/0621; H03H17/0628; H04; H04L; H04L7/00; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
278 words
Digital filter receiving input digital signals at a rate provided by a first clock at a frequency F and providing output digital signals at a rate provided by a second clock at a frequency f which is a submultiple of F, with said clock at a frequency f being slowed down or sped up when it is no longer synchronous with a remote clock, said filter being of the type having a finite impulse answer and a number of taps which is a multiple X of the ratio between F and f and including a last zero value tap, said filter being characterized in that it comprises: a plurality of accumulators (38, 40, 42), the number of which is equal to said multiple X, for adding during each period of said clock F the product of a predetermined input signal value (S) by one predetermined tap coefficient (H) dependent on the accumulator involved; a processing circuit (32, 34, 36) for loading, during each cycle of said clock F, the product of said input signal value by said tap coefficient into each one of said plurality of accumulators; an output circuit (48) for providing an output signal (P) at a rate f by outputting sequentially the contents of each accumulator at said rate f, and a selecting circuit (44 and Figure 5) for selecting the accumulator the contents of which has been output as said output digital signal, as the accumulator to be loaded first by said processing circuit, whereby the last product which is accumulated in the accumulator to be output is always zero enabling the corresponding time interval to be used for adjustment of said frequency f.
Claim 2
Dependent Claim
278 words
Digital filter receiving input digital signals at a rate provided by a first clock at a frequency F and providing output digital signals at a rate provided by a second clock at a frequency f which is a submultiple of F, with said clock at a frequency f being slowed down or sped up when it is no longer synchronous with a remote clock, said filter being of the type having a finite impulse answer and a number of taps which is a multiple X of the ratio between F and f and including a last zero value tap, said filter being characterized in that it comprises: a plurality of accumulators (38, 40, 42), the number of which is equal to said multiple X, for adding during each period of said clock F the product of a predetermined input signal value (S) by one predetermined tap coefficient (H) dependent on the accumulator involved; a processing circuit (32, 34, 36) for loading, during each cycle of said clock F, the product of said input signal value by said tap coefficient into each one of said plurality of accumulators; an output circuit (48) for providing an output signal (P) at a rate f by outputting sequentially the contents of each accumulator at said rate f, and a selecting circuit (44 and Figure 5) for selecting the accumulator the contents of which has been output as said output digital signal, as the accumulator to be loaded first by said processing circuit, whereby the last product which is accumulated in the accumulator to be output is always zero enabling the corresponding time interval to be used for adjustment of said frequency f.
Claim 3
Dependent Claim
80 words
Digital filter according to claim 1 wherein said first clock at frequency F and said second clock at frequency f are issued from a basic oscillator at frequency XF so that, during a period of said first clock which is divided into X cycles of said oscillator, each of said plurality of accumulators (38, 40, 42) is loaded, within one of said cycles, with the product of the same input digital signal by a different tap coefficient of said filter.
Claim 4
Dependent Claim
91 words
Digital filter according to claim 2 wherein, when said second clock (f) is synchronized to said remote clock by a slowing down action, said first clock (F) is adjusted by adding one cycle of said oscillator to a period of said first clock, whereby said output signal (P) which is output from said accumulator at the end of said period is not erroneous due to said slowing down action since the last product which is accumulated twice in said accumulator involves said last zero value and therefore is equal to zero.
Claim 5
Dependent Claim
88 words
Digital filter according to claim 2 wherein, when said second clock (f) is synchronized to said remote clock by a speeding up action, said first clock (F) is adjusted by skipping a cycle of said oscillator in a period of said first clock, whereby said output signal (P) which is output from said accumulator at the end of said period is not erroneous due to said speeding up action since the last product skipped by this action involves said last zero value and therefore is equal to zero.
Claim 6
Dependent Claim
89 words
Digital filter according to claim 2 comprising a first zero value tap and wherein, when said second clock (f) is synchronized to said remote clock by a slowing down action, said first clock (F) is adjusted by delaying by three cycles of said oscillator the output of said output signal (P) from said accumulator, whereby said output signal is not erroneous due to said slowing down action since the last product which is accumulated in said accumulator involves said first zero value coefficient and therefore is equal to zero.
Claim 7
Dependent Claim
88 words
Digital filter according to claim 2 wherein, when said second clock (f) is synchronized to said remote clock by a speeding up action, said first clock (F) is adjusted by advancing by three cycles of said oscillator the output of said output signal (P) from said accumulator, whereby said output signal is not erroneous due to said speeding up action since the last product, which would have been accumulated in the absence of said speeding up action, involves said last zero value and therefore is equal to zero.
Claim 8
Dependent Claim
55 words
Digital filter according to any one of the preceding claims being used in a Sigma-delta analog-to-digital converter, and wherein said input digital signals are a string of bits received from a Sigma-delta coder (10) at said frequency f, and said output digital signals are digital words representing PCM samples produced at the sampling frequency f.
Claim 9
Dependent Claim
143 words
Digital filter according to any one of the preceding claims further comprising a control circuit providing control signals to said accumulators (38, 40, 42° said processing circuit (32, 34, 36), said output circuit (48) and said selecting circuit (44), said control circuit including: - a cycle counter (60) for generating output pulses corresponding to said first clock F in response to input pulses corresponding to said second clock f, said output pulses taking into account the slowing down or speeding up actions on said input pulses; - a window counter (62) for generating window signals corresponding to windows each determining the order said accumulators are loaded during a period of said clock F, in response to the output signal from on accumulator, and - a logic circuit (72) for generating said control signals in response to said output pulses and said window signals.
Claim 10
Dependent Claim
42 words
Digital filter according to any one of the preceding claims wherein said first clock has frequency F = 864 kHz, said second clock has a frequency f = 14.4 kHz, said filter being of the type Sinc³ including 3F/f = 180 taps.
Claim 11
Dependent Claim
19 words
Digital filter according to any one of the preceding claims being used in the analog-to-digital converter of a modem.
References Cited (Backward Citations)
US3796004A
Cited
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