EP0355466A2
Expired / Lapsed
EP
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Integrated circuit with clock generator circuit
Assignee: Motorola Solutions Inc
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Filing: 1989-07-27
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Granted: —
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Expires: 2009-07-27
Abstract
Abstract A microprocessor (10) or other integrated circuit including a clock generator circuit which is dependent on an externally-provided reference signal (XTALCLK) includes the capability of detecting the loss of this externally-provided reference signal and producing an alternate clock signal despite the loss of the reference. In a particular embodiment, the clock generator comprises a phase locked loop frequency synthesizer (23-27) which normally relies on an external crystal oscillator for its reference frequency signal. The generator includes a circuit (22) for detecting abnormalities in the crystal signal and switching the voltage controlled oscillator of the frequency synthesizer to an internally-generated reference voltage. In the particular embodiment, the clock generator is also capable of producing a reset signal in response to the loss of the reference signal.
Inventors
- 👤 Mark W. Mcdermott
- 👤 Antone L. Fourcroy
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 23:59
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/14; G; G01; G01R; G01R29/00; G01R29/02; G01R29/027; G01R29/0273; G06; G06F; G06F1/00; G06F1/04
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
107 words
An integrated circuit comprising: clock signal generator means (22-28) for receiving a reference frequency signal and for generating a clock signal of a first predetermined frequency in response to the reference frequency signal; wherein the improvement comprises: loss of reference signal detect means (22) for receiving the reference frequency signal and for producing a loss of reference output signal in response to a predetermined condition of the reference frequency signal; and the clock signal generator means being responsive to the loss of reference output of the loss of reference signal detect means for generating a clock signal of a second frequency different from the first predetermined frequency.
Claim 2
Dependent Claim
107 words
An integrated circuit comprising: clock signal generator means (22-28) for receiving a reference frequency signal and for generating a clock signal of a first predetermined frequency in response to the reference frequency signal; wherein the improvement comprises: loss of reference signal detect means (22) for receiving the reference frequency signal and for producing a loss of reference output signal in response to a predetermined condition of the reference frequency signal; and the clock signal generator means being responsive to the loss of reference output of the loss of reference signal detect means for generating a clock signal of a second frequency different from the first predetermined frequency.
Claim 3
Dependent Claim
90 words
An integrated circuit according to claim 1 wherein the loss of reference signal detect means further comprises: first means (55-59) for detecting the occurrence of a period of predetermined length during which the reference frequency signal remains in a first predetermined state; and second means (70-74) for detecting the occurrence of a period of predetermined length during which the reference frequency signal remains in a second predetermined state; and third means (60) for producing the loss of reference output signal in response to either of said first and second means.
Claim 4
Dependent Claim
134 words
An integrated circuit according to claim 1 wherein the clock signal generator further comprises: an oscillator circuit (21) coupled to a crystal oscillator external to the integrated circuit, an output of the oscillator comprising the reference frequency signal; a phase locked loop frequency synthesizer (23, 24, 25, 26, 27) comprising an input coupled to the output of the oscillator circuit, an output of the phase locked loop frequency synthesizer comprising a clock signal having a frequency related to the frequency of the reference frequency signal, the phase locked loop frequency synthesizer further comprising an input coupled to an output of the loss of reference signal detect means and being capable of generating a clock signal having a frequency unrelated to the frequency of the reference frequency signal in response to the signal received therefrom.
Claim 5
Dependent Claim
64 words
4 An integrated circuit according to claim 3 further comprising: reset means (83, 85, 87) for receiving the loss of reference output signal from the loss of reference signal detect means and for selectably producing a reset signal in response thereto; and control means (RSTEN) for controlling whether the reset means generates the reset signal in response to the loss of reference output signal.
Claim 6
Dependent Claim
42 words
An integrated circuit according to claim 3 wherein: the phase locked loop frequency synthesizer further comprises a programmable divider (27); and the loss of reference frequency detect means is responsive to the programming of the programmable divider to produce an output signal.
Claim 7
Dependent Claim
109 words
A microprocessor (10) comprising clock signal generator means (22-28) for receiving a reference frequency signal and for generating a clock signal of a first predetermined frequency in response to the reference frequency signal, the clock signal generator means further comprising: loss of reference signal detect means (22)for receiving the reference frequency signal and for producing a loss of reference output signal in response to a predetermined condition of the reference frequency signal; and the clock signal generator means being responsive to the loss of reference output of the loss of reference signal detect means for generating a clock signal of a second frequency different from the first predetermined frequency.
Claim 8
Dependent Claim
109 words
A microprocessor (10) comprising clock signal generator means (22-28) for receiving a reference frequency signal and for generating a clock signal of a first predetermined frequency in response to the reference frequency signal, the clock signal generator means further comprising: loss of reference signal detect means (22)for receiving the reference frequency signal and for producing a loss of reference output signal in response to a predetermined condition of the reference frequency signal; and the clock signal generator means being responsive to the loss of reference output of the loss of reference signal detect means for generating a clock signal of a second frequency different from the first predetermined frequency.
Claim 9
Dependent Claim
89 words
A microprocessor according to claim 6 wherein the loss of reference signal detect means further comprises: first means (55-59) for detecting the occurrence of a period of predetermined length during which the reference frequency signal remains in a first predetermined state; and second means (70-74) for detecting the occurrence of a period of predetermined length during which the reference frequency signal remains in a second predetermined state; and third means (60) for producing the loss of reference output signal in response to either of said first and second means.
Claim 10
Dependent Claim
133 words
A microprocessor according to claim 6 wherein the clock signal generator further comprises: an oscillator circuit (21) coupled to a crystal oscillator external to the integrated circuit, an output of the oscillator comprising the reference frequency signal; a phase locked loop frequency synthesizer (23, 24, 25, 26, 27) comprising an input coupled to the output of the oscillator circuit, an output of the phase locked loop frequency synthesizer comprising a clock signal having a frequency related to the frequency of the reference frequency signal, the phase locked loop frequency synthesizer further comprising an input coupled to an output of the loss of reference signal detect means and being capable of generating a clock signal having a frequency unrelated to the frequency of the reference frequency signal in response to the signal received therefrom.
Claim 11
Dependent Claim
61 words
A microprocessor according to claim 8 further comprising: reset means (83, 85, 87) for receiving the loss of reference output signal from the loss of reference signal detect means and for selectably producing a reset signal in response thereto; and control means (RSTEN)for controlling whether the reset means generates the reset signal in response to the loss of reference output signal.
Claim 12
Dependent Claim
41 words
A microprocessor according to claim 8 wherein: the phase locked loop frequency synthesizer further comprises a programmable divider (27); and the loss of reference frequency detect means is responsive to the programming of the programmable divider to produce an output signal.
References Cited (Backward Citations)
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