EP0353890A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Information handling centre telecommunication servers
Assignee: International Business Machines Corp
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Filing: 1989-07-14
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Granted: —
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Expires: 2009-07-14
Abstract
Abstract A dual digital signal processor (DSP) provides real time links between multiple time division channels of a digital carrier system (e.g. T-1) and a host data processor. Operating only on digital signals, internally and at its interfaces to the carrier and host systems, the DSP exchanges data and control signalling information with the carrier system and data and control information with the host processor, converting the data in passage to different digital forms. At the interface to the carrier system, signals are received and transmitted in a form adapted to diverse terminal equipment of users remotely linked to the carrier system via the switched public network. At the host interface, signals are transferred and received in a form suited to the data process requirements of the host system (e.g. data bytes directly representing alphanumeric characters). Thus, the DSP acts as the equivalent of multiple different types of modems in performing required conversions. The DSP may also perform processing services in order to reduce the processing burden on the host system (e.g. parity checking of data, detection of specific character functions in data or specific tones in audio signals, selective routing of voice to host storage for voice mail applications, etc.)
Inventors
- 👤 Gordon Taylor Davis
- 👤 Michael George Ho Lung
- 👤 Baiju Dhirajlal Mandalia
- 👤 Rolan Jose Millas
- 👤 Oscar Emilio Ortega
- 👤 Rafael Jose Picon
- 👤 Loran Ray Queen
- 👤 Richard Houston Robinson
- 👤 William Robert Robinson, Jr.
- 👤 Leo Alvin Sharp, Jr.
- 👤 Jan Wouter Van Den Berg
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 03:10
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/12; H04Q; H04Q2213/00; H04Q2213/13034; H04Q2213/1309; H04Q2213/13103; H04Q2213/13107; H04Q2213/13174; H04Q2213/13199; H04Q2213/13213; H04Q2213/13215; H04Q2213/13292; H04Q2213/13377; H04Q2213/13396
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
164 words
A server system for providing information telecommunication services between an information handling centre and multiple diversely equipped user terminals remotely linked to the centre through parts of the public switched telephone network comprising: at least one time division multiplexed digital carrier trunk linking the centre with the public telephone network; the trunk carrying digitised functions which vary according to the characteristics of whichever one of a plurality of potential diverse equipment at the user terminals is currently in communication with the centre, in the digital code determined by the network - i.e., digitised Log PCM signals ; and all-digital signal processing means coupling the centre with the trunk for exchanging signals with time channels on the trunk in diverse forms associated with diversity of equipment at the user terminals in the digital code, for exchanging signals with the centre in forms associated with information processing requirements of the centre, and for converting signals in transit between the centre and trunk into respectively associated forms.
Claim 2
Dependent Claim
164 words
A server system for providing information telecommunication services between an information handling centre and multiple diversely equipped user terminals remotely linked to the centre through parts of the public switched telephone network comprising: at least one time division multiplexed digital carrier trunk linking the centre with the public telephone network; the trunk carrying digitised functions which vary according to the characteristics of whichever one of a plurality of potential diverse equipment at the user terminals is currently in communication with the centre, in the digital code determined by the network - i.e., digitised Log PCM signals ; and all-digital signal processing means coupling the centre with the trunk for exchanging signals with time channels on the trunk in diverse forms associated with diversity of equipment at the user terminals in the digital code, for exchanging signals with the centre in forms associated with information processing requirements of the centre, and for converting signals in transit between the centre and trunk into respectively associated forms.
Claim 3
Dependent Claim
226 words
A system as claimed in claim 1, wherein the signal processing means comprises: first digital signal processing means (DSP's) interfacing with the centre, and second digital signal processing means interfacing with the trunk channels; first and second random access memory (RAM) arrays, one (D-RAM array) allocated for storing data and the other (I-RAM array) reserved for holding microinstructions executable by both signal processing means; means cyclically coupling the first and second signal processing means with the memory arrays in time-staggered fashion whereby the processing means alternate in fetching instructions and data from the arrays and alternate in performing operations relative to the data as directed by the instructions; interruption control means coupling the processing means for enabling the first and second processing means to exchange interrupt requests, and for enabling the first processing means and centre to exchange interrupt requests; and means responsive to interruption requests presented by the interruption control means for enabling the first and second processing means to exchange data through the data holding array, whereby the first processing means may process data prepared by the centre for one of the user terminals and the second means may further process the data so that each the processing means partially converts the signal form of the data to prepare the data for transmission to the user terminal via a channel on the digital trunk.
Claim 4
Dependent Claim
259 words
A system as claimed in claim 1, wherein the centre includes a host data processing system, and the all-digital signal processing means comprises first and second digital signal processors (DSP' s) a random access instruction storing memory (I-RAM) coupled to both the DSP's for holding instructions to be used by both and coupled to the host system for receiving instruction program loads for the DSP's from the host system, a random access data storing memory (D-RAM) coupled to both DSP's for holding data to be accessed by dither or both DSP's and coupled to both the host system and the trunk for exchanging data with the host system and the trunk; the I-RAM and D-RAM memories having recurrent cycles of accessibility in which alternate cycles are normally allocated to the first and second DSP's in an interleaved manner, so that each DSP can retrieve instructions from I-RAM without interrupting or slowing operations in the other DSP and so that each DSP can fetch data from D-RAM and write data to D-RAM without interrupting or slowing operations in the other DSP; and cycle steal control means coupled to the DSP's, D-RAM, the host system and the trunk for determining when a cycle of access to the D-RAM is not required by either DSP, and for selectively allocating the cycle to either the host system or the trunk, whereby data can be exchanged between the host system and D-RAM and between D-RAM and trunk in a cycle steal mode having the effect of not interrupting or slowing operations in either DSP.
Claim 5
Dependent Claim
53 words
A system as claimed in claim 3, wherein the I-RAM is configured to store programs of instructions for concurrent execution by both the DSP's, whereby for instance both DSP's may be operated to access a common block of diagnostic instructions in a time interleaved manner, and perform self-diagnostic tests defined by the block.
Claim 6
Dependent Claim
91 words
A system as claimed in claim 4, including direct memory access (DMA) control means coupling the host centre with the D-RAM for providing the host with access to the D-RAM in contention with the DSP's; the DMA and cycle steal control means cooperating whereby when the host system requires access to the D-RAM is preferably provided in a cycle steal mode so as not to interfere with operations of the DSP's, but when such access is unavailable the DMA takes over and provides access while blocking the DSP's from having access.
Claim 7
Independent Claim
38 words
A system as claimed in any of claims 2 to 4, wherein the D-RAM is configured to provide a workspace for each the trunk channel of a size sufficient to sustain modem conversions relative to all channels concurrently.
Claim 8
Dependent Claim
86 words
A system as claimed in claim 6, including means for adapting the signal processing means for performing diverse digital filtering and modem conversion transformations on digital signals en route between the centre and the trunk, and means coupled to the memory arrays for configuring portions of the data storing array as circular buffers such that each buffer is allocatable to an interface to a channel of the trunk and can be used concurrently to sustain both modem and digital filtering transformations relative to data held therein.
Claim 9
Independent Claim
58 words
A system as claimed in any preceding claim, the all-digital processing means including means for selectively handling signals representing digitised speech or sound data; the means including means for applying compression and decompression conversions to the signals whereby the signals can be stored in a compressed form at the centre and transmitted over the trunk in decompressed form.
Claim 10
Independent Claim
54 words
A system as claimed in any preceding claim, the all-digital processing means including means for selectively handling signals representing digitised video image data; the means including means for applying decompression and compression conversions to the data whereby the data is handled in decompressed form at the centre and in compressed form over the trunk.
Claim 11
Dependent Claim
39 words
A system as claimed in claim 2, including means cooperative with the arrays for configuring portions of the arrays into circular buffers dimensioned in accordance with the requirements of signal conversion processes being handled in the signal processing means.
References Cited (Backward Citations)
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