Solenoid drive circuit

Claim 2

A driver circuit which is responsive to an input AC line voltage for providing a drive signal to a load circuit, said driver circuit comprising: a) means for receiving the input AC voltage; b) timing circuit means for producing a timing signal that is synchronized to the AC voltage cycle; c) switch actuated means responsive to said timing signal for generating a control signal for a selected period of time that is related to one cycle of the input AC voltage, said selected time period occurring only during the time that the input AC voltage is in the positive portion of its cycle; d) means for applying said timing signal to said switch actuated control signal generating means; e) switch means for actuating said control signal generating means to produce said control signal; and, f) firing means responsive to said control signal for providing a drive signal to the load circuit during the time period that the control signal is applied to the firing means.

Claim 3

The driver circuit of claim 1 wherein said timing circuit means and said control signal generation means comprise a single integrated circuit chip.

Claim 4

The driver circuit of claim 2 wherein said single integrated circuit chip is a flip-flop.

Claim 5

The driver circuit of claim 1 wherein said switch means comprises a single pole single throw switch.

Claim 6

The driver circuit of claims 1 or 4 wherein only one control signal is produced during a full cycle of the AC voltage even though switch bounce occurs during a portion of the AC voltage cycle.

Claim 7

A driver circuit which is responsive to an input AC line voltage for providing a drive signal to a load circuit, said driver circuit comprising: a) means for receiving the input AC voltage; b) means for providing a DC voltage that is related to the input AC voltage; c) sine wave shaper means for producing a positive edge delayed square wave timing signal in response to DC voltage that is related to the input AC voltage; d) a switch actuated continually clocked flip-­flop means responsive to said timing signal for generating upon the actuation of the flip-­flop means a control signal for a selected time period that is related to one cycle of the input AC voltage, said selected time period occurring only during the time that the input AC voltage is in the positive portion of its cycle; e) means for applying said timing signal to the clock input of said clocked flip-flop means; f) switch means for actuating said continually clocked flip-flop means; and, g) firing means responsive to said control signal for providing a drive signal to the load circuit during the time period that the control signal is applied to the firing means.

Claim 8

A driver circuit which is responsive to an input AC line voltage for providing a drive signal to a load circuit, said driver circuit comprising: a) means for receiving the input AC voltage; b) means for providing a DC voltage that is related to the input AC voltage; c) sine wave shaper means for producing a positive edge delayed square wave timing signal in response to DC voltage that is related to the input AC voltage; d) a switch actuated continually clocked flip-­flop means responsive to said timing signal for generating upon the actuation of the flip-­flop means a control signal for a selected time period that is related to one cycle of the input AC voltage, said selected time period occurring only during the time that the input AC voltage is in the positive portion of its cycle; e) means for applying said timing signal to the clock input of said clocked flip-flop means; f) switch means for actuating said continually clocked flip-flop means; and, g) firing means responsive to said control signal for providing a drive signal to the load circuit during the time period that the control signal is applied to the firing means.

Claim 9

The driver circuit of claim 6 wherein the delayed positive edge of the square wave timing signal is delayed 30 degrees or less from the positive going zero crossing of the input AC voltage.

Claim 10

The driver circuit of claim 7 wherein the delayed positive edge of the square wave timing signal is delayed by 22 degrees to 30 degrees from the positive going zero crossing of the input AC voltage.

Claim 11

The driver circuit of claim 6 wherein the clocked flip-flop means is clocked no more than 30 degrees after the positive going zero crossing of the input AC voltage.

Claim 12

The driver circuit of claim 6 wherein said clocked flip-flop is a D-type flip-flop and wherein actuation of said switch means applies drain voltage to said flip-­flop.

Claim 13

The driver circuit of claim 6 wherein only one control signal is produced during a full cycle of the AC voltage even though switch bounce of said switch means occurs during a portion of the AC voltage cycle.